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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Features
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Facility Data Link Features
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Eight independent T1/E1 transmit and receive framers. Internal DS1 transmit clock synthesis--no external oscillator necessary. Comprehensive alarm reporting and performance monitoring: -- Programmable automatic and on-demand alarm transmission. Automatic facility data link: -- Automatic transmission of ESF performance report message. Common 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s TDM highway. Dual- or single-rail line-side I/O. Supports one second polling interval for performance monitoring.
HDLC or transparent mode. Automatic transmission of the ESF performance report messages (PRM). Detection of the ESF PRM. Detection of the ANSI ESF FDL bit-oriented codes. 64-byte FIFO in both transmit and receive directions. Programmable FIFO full and empty level interrupt. User-programmable microprocessor interface.
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Microprocessor Interface
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33 MHz read and write access. 12-bit address, 8-bit data interface.
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IEEE * Std. 1149.1 JTAG boundary scan.
3.3 V low-power CMOS with 5 V tolerant inputs. Available in 352-pin PBGA.
Intel or Motorola style control interfaces.
Directly addressable internal registers. Programmable interrupts.
T1/E1 Framer Features
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Applications
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Supports T1 framing modes ESF, D4, SLC (R)-96, T1DM DDS. Supports G.704 basic and CRC-4 multiframe format E1 framing and procedures consistent with G.706. Supports unframed transmission format. T1 signaling modes: transparent; ESF 2-state, 4-state, and 16-state; D4 2-state and 4-state; SLC-96 2-state, 4-state, 9-state, and 16-state. E1 signaling modes: transparent and CAS. Alarm reporting and performance monitoring per AT&T, ANSI , and ITU-T standards. Programmable, independent transmit and receive system interfaces at a 2.048 MHz, 4.096 MHz, or 8.192 MHz data rate.
DS3 and E3 port cards for narrowband DXCs. Multiservice switches. High density DS1 and E1 port cards. Frame relay access devices. Byte-synchronous SDH/SONET mapping. SONET and SDH drop alignment. IP and packet routers.
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* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. ANSI is a registered trademark of American National Standards Institute, Inc. Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc.
TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Table of Contents
Contents Page
Features ................................................................................................................................................................... 1 T1/E1 Framer Features ......................................................................................................................................... 1 Facility Data Link Features ....................................................................................................................................... 1 Microprocessor Interface .......................................................................................................................................... 1 Applications .............................................................................................................................................................. 1 Feature Descriptions .............................................................................................................................................. 10 T1/E1 Framer Feature Descriptions .................................................................................................................... 10 Functional Description ............................................................................................................................................ 11 Pin Information ....................................................................................................................................................... 15 LIU-Framer Interface .............................................................................................................................................. 29 LIU-Framer Physical Interface............................................................................................................................. 29 Line Encoding...................................................................................................................................................... 31 DS1: Zero Code Suppression (ZCS)................................................................................................................... 31 CEPT: High-Density Bipolar of Order 3 (HDB3).................................................................................................. 33 Frame Formats ....................................................................................................................................................... 34 T1 Framing Structures......................................................................................................................................... 34 T1 Loss of Frame Alignment (LFA) ..................................................................................................................... 41 T1 Frame Recovery Alignment Algorithms.......................................................................................................... 42 T1 Robbed-Bit Signaling ..................................................................................................................................... 43 CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Structures ................... 45 CEPT 2.048 Basic Frame Structure .................................................................................................................... 46 CEPT Loss of Basic Frame Alignment (LFA) ...................................................................................................... 48 CEPT Loss of Frame Alignment Recovery Algorithm ......................................................................................... 48 CEPT Time Slot 0 CRC-4 Multiframe Structure .................................................................................................. 49 CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA).................................................................................... 50 CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms ..................................................................... 51 CEPT Time Slot 16 Multiframe Structure ............................................................................................................ 55 CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA)......................................................................... 56 CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm.............................................................. 56 CEPT Time Slot 0 FAS/NOT FAS Control Bits....................................................................................................... 56 FAS/NOT FAS Si- and E-Bit Source ................................................................................................................... 56 NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources ..................................................................................... 57 NOT FAS Sa-Bit Sources.................................................................................................................................... 57 Sa Facility Data Link Access ............................................................................................................................... 58 NOT FAS Sa Stack Source and Destination ....................................................................................................... 59 CEPT Time Slot 16 X0--X2 Control Bits............................................................................................................. 61 Signaling Access .................................................................................................................................................... 61 Transparent Signaling ......................................................................................................................................... 61 DS1: Robbed-Bit Signaling.................................................................................................................................. 61 CEPT: Time Slot 16 Signaling............................................................................................................................. 62 Auxiliary Framer I/O Timing ................................................................................................................................... 63 Alarms and Performance Monitoring ...................................................................................................................... 67 Interrupt Generation ............................................................................................................................................ 67 Alarm Definition ................................................................................................................................................... 67 Event Counters Definition ................................................................................................................................... 73 Loopback and Transmission Modes.................................................................................................................... 75 Line Test Patterns ............................................................................................................................................... 78 Receive Line Pattern Monitor--Using Register FRM_SR7 ................................................................................. 80 Automatic and On-Demand Commands ............................................................................................................. 82 Facility Data Link .................................................................................................................................................... 84
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Table of Contents (continued)
Contents Page
Receive Facility Data Link Interface.....................................................................................................................84 Transmit Facility Data Link Interface....................................................................................................................90 HDLC Operation ..................................................................................................................................................91 Transparent Mode................................................................................................................................................93 Diagnostic Modes ................................................................................................................................................95 Phase-Lock Loop Circuit .........................................................................................................................................96 Framer-System Interface ........................................................................................................................................98 DS1 Modes ..........................................................................................................................................................98 CEPT Modes........................................................................................................................................................98 Receive Elastic Store...........................................................................................................................................98 Transmit Elastic Store..........................................................................................................................................98 Concentration Highway Interface ............................................................................................................................98 CHI Parameters ...................................................................................................................................................99 CHI Frame Timing..............................................................................................................................................101 CHI Offset Programming....................................................................................................................................104 JTAG Boundary-Scan Specification ..................................................................................................................... 105 Principle of the Boundary Scan..........................................................................................................................105 Test Access Port Controller ...............................................................................................................................107 Instruction Register ............................................................................................................................................109 Boundary-Scan Register....................................................................................................................................110 BYPASS Register ..............................................................................................................................................110 DCODE Register................................................................................................................................................110 3-State Procedures ............................................................................................................................................110 Microprocessor Interface.......................................................................................................................................111 Overview ............................................................................................................................................................111 Microprocessor Configuration Modes ................................................................................................................111 Microprocessor Interface Pinout Definitions ......................................................................................................112 Microprocessor Clock (MPCLK) Specifications .................................................................................................112 Microprocessor Interface Register Address Map ...............................................................................................113 I/O Timing ..........................................................................................................................................................113 Reset.................................................................................................................................................................... 118 Hardware Reset (Pin C19).................................................................................................................................118 Software Reset/Software Restart.......................................................................................................................118 Interrupt Generation ..............................................................................................................................................118 Register Architecture.............................................................................................................................................119 Global Register Architecture .................................................................................................................................123 Global Register Structure......................................................................................................................................123 Framer Block Interrupt Status Register (GREG0)..............................................................................................123 Framer Block Interrupt Enable Register (GREG1).............................................................................................124 FDL Block Interrupt Status Enable Register (GREG2) ......................................................................................124 FDL Block Interrupt Enable Register (GREG3) .................................................................................................124 Global Control Register (GREG4)......................................................................................................................125 Device ID and Version Registers (GREG5--GREG7) .......................................................................................125 Global Control Register (GREG8)......................................................................................................................126 Global PLLCK Control Register (GREG9) .........................................................................................................127 Framer Register Architecture ................................................................................................................................127 Framer Status/Counter Registers ......................................................................................................................128 Framer Parameter/Control Registers .................................................................................................................141 FDL Register Architecture.....................................................................................................................................168 FDL Parameter/Control Registers ((A00--A0E); (A20--A2E); (B00--B0E); (B20--B2E) (C00--C0E); (C20--C2E); (D00--D0E); (D20--D2E)) .................................................................169 Lucent Technologies Inc. 3
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Preliminary Data Sheet October 2000
Table of Contents (continued)
Contents Page
Register Maps ...................................................................................................................................................... 176 Global Registers................................................................................................................................................ 176 Framer Parameter/Control Registers (Read-Write)........................................................................................... 177 Receive Framer Signaling Registers (Read-Only) ............................................................................................ 179 Framer Unit Parameter Register Map ............................................................................................................... 180 Transmit Signaling Registers (Read/Write) ....................................................................................................... 183 Facility Data Link Parameter/Control and Status Registers (Read-Write)......................................................... 184 Absolute Maximum Ratings.................................................................................................................................. 185 Operating Conditions............................................................................................................................................ 185 Handling Precautions ........................................................................................................................................... 185 Electrical Characteristics ...................................................................................................................................... 186 Logic Interface Characteristics .......................................................................................................................... 186 Power Supply Bypassing...................................................................................................................................... 186 Outline Diagram.................................................................................................................................................... 187 352-Pin PBGA ................................................................................................................................................... 187 Ordering Information............................................................................................................................................. 188
Figures
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Figure 1. TFRA08C13 Block Diagram (One of Eight Channels)............................................................................. 11 Figure 2. TFRA08C13 Block Diagram: Receive Section (One of Eight Channels)................................................. 13 Figure 3. TFRA08C13 Block Diagram: Transmit Section (One of Eight Channels) ................................................ 14 Figure 4. Pin Assignment ....................................................................................................................................... 15 Figure 5. Block Diagram of Framer Line Interface .................................................................................................. 29 Figure 6. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing ......................... 30 Figure 7. T1 Frame Structure ................................................................................................................................. 34 Figure 8. T1 Transparent Frame Structure ............................................................................................................. 35 Figure 9. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections ......................... 37 Figure 10. SLC-96 Frame Format........................................................................................................................... 37 Figure 11. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe Structures .......................................................................................................................... 45 Figure 12. CEPT Transparent Frame Structure ...................................................................................................... 47 Figure 13. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer................................... 52 Figure 14. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991)..................................................... 54 Figure 15. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT Mode.................................................................................................................... 58 Figure 16. Transmit and Receive Sa Stack Accessing Protocol ............................................................................. 60 Figure 17. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode .............................................. 63 Figure 18. Timing Specification for TFS, TLCK, and TPD in DS1 Mode ................................................................ 63 Figure 19. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode ........................................... 64 Figure 20. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode ............................. 64 Figure 21. Timing Specification for RCRCMFS in CEPT Mode.............................................................................. 65 Figure 22. Timing Specification for TFS, TLCK, and TPD in CEPT Mode.............................................................. 65 Figure 23. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode ................................................ 66 Figure 24. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode .......................................... 66 Figure 25. Relation Between RLCK1 and Interrupt (Pin AD8)................................................................................ 67 Figure 26. Timing for Generation of LOPLLCK (Pin F25)....................................................................................... 69 Figure 27. The T and V Reference Points for a Typical CEPT E1 Application........................................................ 72 Figure 28. Loopback and Test Transmission Modes............................................................................................... 77 4 Lucent Technologies Inc.
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Figures Page
Figure 29. 20-Stage Shift Register Used to Generate the Quasi-Random Signal ..................................................78 Figure 30. 15-Stage Shift Register Used to Generate the Pseudorandom Signal ..................................................79 Figure 31. TFRA08C13 Facility Data Link Access Timing of the Transmit and Receive Framer Sections ..............84 Figure 32. Block Diagram for the Receive Facility Data Link Interface....................................................................85 Figure 33. Block Diagram for the Transmit Facility Data Link Interface ...................................................................90 Figure 34. Local Loopback Mode ............................................................................................................................95 Figure 35. Remote Loopback Mode ........................................................................................................................96 Figure 36. TFRA08C13 Phase Detector Circuitry ...................................................................................................97 Figure 37. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0--bit 2 = 100 (Binary)) ..........101 Figure 38. CHIDTS Mode Concentration Highway Interface Timing .....................................................................102 Figure 39. Associated Signaling Mode Concentration Highway Interface Timing .................................................103 Figure 40. CHI Timing with ASM and CHIDTS Enabled .......................................................................................103 Figure 41. TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 0 (CEX = 3 and CER = 4, Respectively) ...............................................................................................................104 Figure 42. Receive CHI (RCHIDATA) Timing.........................................................................................................105 Figure 43. Transmit CHI (TCHIDATA) Timing ........................................................................................................105 Figure 44. Block Diagram of the TFRA08C13's Boundary-Scan Test Logic .........................................................106 Figure 45. BS TAP Controller State Diagram ........................................................................................................107 Figure 46. Mode 1--Read Cycle Timing (MPMODE = 0) .....................................................................................116 Figure 47. Mode 1--Write Cycle Timing (MPMODE = 0)......................................................................................116 Figure 48. Mode 3--Read Cycle Timing (MPMODE = 1) .....................................................................................117 Figure 49. Mode 3--Write Cycle Timing (MPMODE = 1)......................................................................................117
Tables
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Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order.......................................................................16 Table 2. Pin Descriptions........................................................................................................................................18 Table 3. AMI Encoding ...........................................................................................................................................31 Table 4. DS1 ZCS Encoding...................................................................................................................................32 Table 5. DS1 B8ZS Encoding.................................................................................................................................32 Table 6. ITUHDB3 Coding ......................................................................................................................................33 Table 7. T-Carrier Hierarchy....................................................................................................................................34 Table 8. D4 Superframe Format .............................................................................................................................36 Table 9. DDS Channel-24 Format ..........................................................................................................................37 Table 10. SLC-96 Data Link Block Format .............................................................................................................38 Table 11. SLC-96 Line Switch Message Codes .....................................................................................................39 Table 12. Transmit and Receive SLC-96 Stack Structure.......................................................................................39 Table 13. Extended Superframe (ESF) Structure...................................................................................................40 Table 14. T1 Loss of Frame Alignment Criteria ......................................................................................................41 Table 15. T1 Frame Alignment Procedures ............................................................................................................42 Table 16. Robbed-Bit Signaling Options.................................................................................................................43 Table 17. SLC-96 9-State Signaling Format ...........................................................................................................43 Table 18.16-State Signaling Format .......................................................................................................................44 Table 19. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame ......................................................46 Table 20. ITU CRC-4 Multiframe Structure.............................................................................................................49 Table 21. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure ........................................55 Table 22. Transmit and Receive Sa Stack Structure...............................................................................................59 Table 23. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames ...........................................62 Table 24. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels....................................62
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Table 25. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT..................................................... 62 Table 26. Red Alarm or Loss of Frame Alignment Conditions ............................................................................... 68 Table 27. Remote Frame Alarm Conditions ........................................................................................................... 68 Table 28. Alarm Indication Signal Conditions ........................................................................................................ 69 Table 29. Sa6 Bit Coding Recognized by the Receive Framer. ............................................................................. 71 Table 30. Sa6 Bit Coding of NT1 Interface Events Recognized by the Receive Framer........................................ 71 Table 31. AUXP Synchronization and Clear Synchronization Process.................................................................. 72 Table 32. Event Counters Definition ...................................................................................................................... 73 Table 33. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function of Activating the Primary Loopback Modes .......................................................................................... 76 Table 34. Register FRM_PR69 Test Patterns ........................................................................................................ 79 Table 35. Register FRM_PR70 Test Patterns ........................................................................................................ 80 Table 36. Automatic Enable Commands................................................................................................................ 82 Table 37. On-Demand Commands ........................................................................................................................ 83 Table 38. Receive ANSI Code ............................................................................................................................... 86 Table 39. Performance Report Message Structure................................................................................................ 86 Table 40. FDL Performance Report Message Field Definition............................................................................... 87 Table 41. Octet Contents and Definition ................................................................................................................ 87 Table 42. Receive Status of Frame Byte................................................................................................................ 88 Table 43. HDLC Frame Format.............................................................................................................................. 91 Table 44. Receiver Operation in Transparent Mode............................................................................................... 94 Table 45. Summary of the TFRA08C13's Concentration Highway Interface Parameters ...................................... 99 Table 46. Programming Values for TOFF[2:0] and ROFF[2:0] when CMS = 0 .................................................... 104 Table 47. TAP Controller States in the Data Register Branch.............................................................................. 108 Table 48. TAP Controller States in the Instruction Register Branch..................................................................... 108 Table 49. TFRA08C13's Boundary-Scan Instructions ......................................................................................... 109 Table 50. IDCODE Register................................................................................................................................. 110 Table 51. Microprocessor Configuration Modes .................................................................................................. 111 Table 52. Mode [1 and 3] Microprocessor Pin Definitions.................................................................................... 112 Table 53. Microprocessor Input Clock Specifications .......................................................................................... 112 Table 54. TFRA08C13 Register Address Map..................................................................................................... 113 Table 55. Microprocessor Interface I/O Timing Specifications ............................................................................. 114 Table 56. Status Register and Corresponding Interrupt Enable Register for Functional Blocks.......................... 118 Table 57. Asserted Value and Deasserted State for GREG4 Bit 4 and Bit 6 Logic Combinations ...................... 118 Table 58. Register Summary ............................................................................................................................... 119 Table 59. Global Register Set (0x000--0x009) ................................................................................................... 123 Table 60. Framer Block Interrupt Status Register (GREG0) (000)....................................................................... 123 Table 61. Framer Block Interrupt Enable Register (GREG1) (001)...................................................................... 124 Table 62. FDL Block Interrupt Status Register (GREG2) (002) ........................................................................... 124 Table 63. FDL Block Interrupt Enable Register (GREG3) (003) .......................................................................... 124 Table 64. Global Control Register (GREG4) (004) .............................................................................................. 125 Table 65. Device ID and Version Registers (GREG5--GREG7) (005--007) ...................................................... 125 Table 66. Global Control Register (GREG8) (008) .............................................................................................. 126 Table 67. Global PLLCK Control Register (GREG9) (009) .................................................................................. 127 Table 68. Framer Status and Control Blocks Address Range (Hexadecimal)...................................................... 127 Table 69. Interrupt Status Register (FRM_SR0) (Y00) ........................................................................................ 128 Table 70. Facility Alarm Condition Register (FRM_SR1) (Y01) ........................................................................... 129 Table 71. Remote End Alarm Register (FRM_SR2) (Y02) .................................................................................. 130 Table 72. Facility Errored Event Register-1 (FRM_SR3) (Y03) ........................................................................... 131
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Table 73. Facility Event Register-2 (FRM_SR4) (Y04) ........................................................................................132 Table 74. Exchange Termination and Exchange Termination Remote End Interface Status Register (FRM_SR5) (Y05) ..............................................................................................133 Table 75. Network Termination and Network Termination Remote End Interface Status Register (FRM_SR6) (Y06)......................................................................................................134 Table 76. Facility Event Register (FRM_SR7) (Y07) ............................................................................................135 Table 77. Bipolar Violation Counter Registers (FRM_SR8--FRM_SR9) (Y08--Y09) .........................................135 Table 78. Framing Bit Error Counter Registers (FRM_SR10--FRM_SR11) (Y0A--Y0B)....................................135 Table 79. CRC Error Counter Registers (FRM_SR12--FRM_SR13) (Y0C--Y0D) .............................................136 Table 80. E-Bit Counter Registers (FRM_SR14--FRM_SR15) (Y0E--Y0F) .......................................................136 Table 81. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16--FRM_SR17) (Y10--Y11) ..............136 Table 82. E Bit at NT1 from NT2 Counter (FRM_SR18--FRM_SR19) (Y12--Y13) ............................................136 Table 83. ET Errored Seconds Counter (FRM_SR20--FRM_SR21) (Y14--Y15) ...............................................137 Table 84. ET Bursty Errored Seconds Counter (FRM_SR22--FRM_SR23) (Y16--Y17) ....................................137 Table 85. ET Severely Errored Seconds Counter (FRM_SR24--FRM_SR25) (Y18--Y19) ................................137 Table 86. ET Unavailable Seconds Counter (FRM_SR26--FRM_SR27) (Y1A--Y1B)........................................137 Table 87. ET-RE Errored Seconds Counter (FRM_SR28--FRM_SR29) (Y1C--Y1D) ........................................137 Table 88. ET-RE Bursty Errored Seconds Counter (FRM_SR30--FRM_SR31) (Y1E--Y1F)..............................137 Table 89. ET-RE Severely Errored Seconds Counter (FRM_SR32--FRM_SR33) (Y20--Y21)...........................137 Table 90. ET-RE Unavailable Seconds Counter (FRM_SR34--FRM_SR35) (Y22--Y23) ...................................138 Table 91. NT1 Errored Seconds Counter (FRM_SR36--FRM_SR37) (Y24--Y25).............................................138 Table 92. NT1 Bursty Errored Seconds Counter (FRM_SR38--FRM_SR39) (Y26--Y27)..................................138 Table 93. NT1 Severely Errored Seconds Counter (FRM_SR40--FRM_SR41) (Y28--Y29) ..............................138 Table 94. NT1 Unavailable Seconds Counter (FRM_SR42--FRM_SR43) (Y2A--Y2B)......................................138 Table 95. NT1-RE Errored Seconds Counter (FRM_SR44--FRM_SR45) (Y2C--Y2D) .....................................138 Table 96. NT1-RE Bursty Errored Seconds Counter (FRM_SR46--FRM_SR47) (Y2E--Y2F) ...........................138 Table 97. NT1-RE Severely Errored Seconds Counter (FRM_SR48--FRM_SR49) (Y30--Y31) ........................138 Table 98. NT1-RE Unavailable Seconds Counter (FRM_SR50--FRM_SR51) (Y32--Y33) ................................139 Table 99. Receive NOT-FAS TS0 Register (FRM_SR52) (Y34) ...........................................................................139 Table 100. Receive Sa Register (FRM_SR53) (Y35) ...........................................................................................139 Table 101. SLC-96 FDL Receive Stack (FRM_SR54--FRM_SR63) (Y36--Y3F) ...............................................139 Table 102. CEPT Sa Receive Stack (FRM_SR54--FRM_SR63) (Y36--Y3F) ....................................................140 Table 103. Transmit Framer ANSI Performance Report Message Status Register Structure ..............................140 Table 104. Received Signaling Registers: DS1 Format (FRM_RSR0--FRM_RSR23) (Y40--Y58) ....................140 Table 105. Receive Signaling Registers: CEPT Format (FRM_RSR0--FRM_RSR31) (Y40--Y5F) ...................141 Table 106. Summary of Interrupt Group Enable Registers (FRM_PR0--FRM_PR7) (Y60--Y67) ......................141 Table 107. Primary Interrupt Group Enable Register (FRM_PR0) (Y60) .............................................................142 Table 108. Interrupt Enable Register (FRM_PR1) (Y61) ......................................................................................142 Table 109. Interrupt Enable Register (FRM_PR2) (Y62) ......................................................................................142 Table 110. Interrupt Enable Register (FRM_PR3) (Y63) ......................................................................................142 Table 111. Interrupt Enable Register (FRM_PR4) (Y64) ......................................................................................143 Table 112. Interrupt Enable Register (FRM_PR5) (Y65) ......................................................................................143 Table 113. Interrupt Enable Register (FRM_PR6) (Y66) ......................................................................................143 Table 114. Interrupt Enable Register (FRM_PR7) (Y67) ......................................................................................143 Table 115. Framer Mode Bits Decoding (FRM_PR8) (Y68) .................................................................................143 Table 116. Line Code Option Bits Decoding (FRM_PR8) (Y68)...........................................................................144 Table 117. CRC Option Bits Decoding (FRM_PR9) (Y69) ...................................................................................144 Table 118. Alarm Filter Register (FRM_PR10) (Y6A)...........................................................................................145 Table 119. Errored Event Threshold Definition.....................................................................................................145 Table 120. Errored Second Threshold Register (FRM_PR11) (Y6B) ...................................................................146
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Table 121. Severely Errored Second Threshold Registers (FRM_PR12--FRM_PR13) (Y6C--Y6D) ................ 146 Table 122. ET1 Errored Event Enable Register (FRM_PR14) (Y6E)................................................................... 146 Table 123. ET1 Remote End Errored Event Enable Register (FRM_PR15) (Y6F).............................................. 146 Table 124. NT1 Errored Event Enable Register (FRM_PR16) (Y70)................................................................... 147 Table 125. NT1 Remote End Errored Event Enable Registers (FRM_PR17--FRM_PR18) (Y71--Y72)............ 147 Table 126. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (Y73)........... 147 Table 127. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (Y73)........... 148 Table 128. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (Y74) ............................................. 148 Table 129. Framer FDL Control Command Register (FRM_PR21) (Y75) ........................................................... 149 Table 130. Framer Transmit Line Idle Code Register (FRM_PR22) (Y76)........................................................... 149 Table 131. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (Y77) .............................................. 149 Table 132. Primary Time-Slot Loopback Address Register (FRM_PR24) (Y78) ................................................. 150 Table 133. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7--5 ......................................................... 150 Table 134. Secondary Time-Slot Loopback Address Register (FRM_PR25) (Y79) ............................................ 151 Table 135. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6--5 ......................................................... 151 Table 136. Framer Reset and Transparent Mode Control Register (FRM_PR26) (Y7A) ..................................... 152 Table 137. Transmission of Remote Frame Alarm and CEPT Automatic Transmission of A Bit = 1 Control Register (FRM_PR27) (Y7B) ....................................................................... 153 Table 138. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (Y7C)............................. 154 Table 139. Sa4--Sa8 Source Register (FRM_PR29) (Y7D) ............................................................................... 154 Table 140. Sa Bits Source Control for Bit 5--Bit 7 in FRM_PR29 ....................................................................... 155 Table 141. Sa4--Sa8 Control Register (FRM_PR30) (Y7E) ............................................................................... 155 Table 142. Sa Transmit Stack (FRM_PR31--FRM_PR40) (Y7F--Y88).............................................................. 156 Table 143. SLC-96 Transmit Stack (FRM_PR31--FRM_PR40) (Y7F--Y88) ...................................................... 156 Table 144. Transmit SLC-96 FDL Format ............................................................................................................ 156 Table 145. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register (FRM_PR41) (Y89) ................................................................................................................ 157 Table 146. Framer Exercise Register (FRM_PR42) (Y8A) .................................................................................. 157 Table 147. Framer Exercises, FRM_PR42 Bit 5--Bit 0 (Y8A) ............................................................................. 158 Table 148. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (Y8B)........... 159 Table 149. Signaling Mode Register (FRM_PR44) (Y8C) ................................................................................... 160 Table 150. CHI Common Control Register (FRM_PR45) (Y8D).......................................................................... 161 Table 151. CHI Common Control Register (FRM_PR46) (Y8E) .......................................................................... 162 Table 152. CHI Transmit Control Register (FRM_PR47) (Y8F) ........................................................................... 162 Table 153. CHI Receive Control Register (FRM_PR48) (Y90) ............................................................................ 162 Table 154. CHI Transmit Time-Slot Enable Registers (FRM_PR49--FRM_PR52) (Y91--Y94) ......................... 163 Table 155. CHI Receive Time-Slot Enable Registers (FRM_PR53--FRM_PR56) (Y95--Y98) .......................... 163 Table 156. CHI Transmit Highway Select Registers (FRM_PR57--FRM_PR60) (Y99--Y9C)............................ 163 Table 157. CHI Receive Highway Select Registers (FRM_PR61--FRM_PR64) (Y9D--YA0) ............................ 163 Table 158. CHI Transmit Control Register (FRM_PR65) (YA1)............................................................................ 164 Table 159. CHI Receive Control Register (FRM_PR66) (YA2) ............................................................................ 164 Table 160. Auxiliary Pattern Generator Control Register (FRM_PR69) (YA5) ..................................................... 165 Table 161. Pattern Detector Control Register (FRM_PR70) (YA6) ...................................................................... 166 Table 162. Transmit Signaling Registers: DS1 Format (FRM_TSR0--FRM_TSR23) (YE0--YF7) ..................... 167 Table 163. Transmit Signaling Registers: CEPT Format (FRM_TSR0--FRM_TSR31) (YE0--YFF) .................. 167 Table 164. FDL Register Set ((A00--A0E); (A20--A2E); (B00--B0E); (B20--B2E) (C00--C0E); (C20--C2E); (D00--D0E); (D20--D2E))..................................................................................... 168 Table 165. FDL Configuration Control Register (FDL_PR0) (A00; A20; B00; B20; C00; C20; D00; D20) .......... 169 Table 166. FDL Control Register (FDL_PR1) (A01; A21; B01; B21; C01; C21; D01; D21)................................. 169
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Table of Contents (continued)
Tables Page
Table 167. FDL Interrupt Mask Control Register (FDL_PR2) (A02; A22; B02; B22; C02; C22; D02; D22) .........170 Table 168. FDL Transmitter Configuration Control Register (FDL_PR3) (A03; A23; B03; B23; C03; C23; D03; D23).......................................................................................................171 Table 169. FDL Transmitter FIFO Register (FDL_PR4) (A04; A24; B04; B24; C04; C24; D04; D24) ..................171 Table 170. FDL Transmitter Idle Character Mask Register (FDL_PR5) (A05; A25; B05; B25; C05; C25; D05; D25).......................................................................................................171 Table 171. FDL Receiver Interrupt Level Control Register (FDL_PR6) (A06; A26; B06; B26; C06; C26; D06; D26).......................................................................................................172 Table 172. FDL Register FDL_PR7......................................................................................................................172 Table 173. FDL Receiver Match Character Register (FDL_PR8) (A08; A28; B08; B28; C08; C28; D08; D28) ...172 Table 174. FDL Transparent Control Register (FDL_PR9) (A09; A29; B09; B29; C09; C29; D09; D29)..............173 Table 175. FDL Transmit ANSI ESF Bit Codes (FDL_PR10) (A0A; A2A; B0A; B2A; C0A; C2A; D0A; D2A).......173 Table 176. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) (A0B; A2B; B0B; B2B; C0B; C2B; D0B; D2B) ...................................................................................................174 Table 177. FDL Transmitter Status Register (FDL_SR1) (A0C; A2C; B0C; B2C; C0C; C2C; D0C; D2C) ...........175 Table 178. FDL Receiver Status Register (FDL_SR2) (A0D; A2D; B0D; B2D; C0D; C2D; D0D; D2D) ..............175 Table 179. Receive ANSI FDL Status Register (FDL_SR3) (A0E; A2E; B0E; B2E; C0E; C2E; D0E; D2E) ........175 Table 180. FDL Receiver FIFO Register (FDL_SR4) (A07; A27; B07; B27; C07; C27; D07; D27)......................175 Table 181. Global Register Set.............................................................................................................................176 Table 182. Framer Unit Status Register Map .......................................................................................................177 Table 183. Receive Signaling Registers Map .......................................................................................................179 Table 184. Framer Unit Parameter Register Map .................................................................................................180 Table 185. Transmit Signaling Registers Map ......................................................................................................183 Table 186. Facility Data Link Register Map ..........................................................................................................184 Table 187. ESD Threshold Voltage.......................................................................................................................185 Table 188. Logic Interface Characteristics (TA = -40 C to +85 C, VDD = 3.3 V 5%, VSS = 0).........................186
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2. Errored frame alignment signals. 3. Errored CRC checksum block. 4. CEPT: received E bit = 0. 5. Errored, severely errored, and unavailable seconds. -- Selectable errored event monitoring for errored and severely errored seconds processing with programmable thresholds for errored and severely errored second monitoring. -- CEPT: Selectable automatic transmission of E bit to the line. -- CEPT: Sa6 coded remote end CRC-4 error E bit = 0 events. -- Programmable automatic and on-demand alarm transmission: 1. Automatic transmission of remote frame alarm to the line while in loss of frame alignment state. 2. Automatic transmission of alarm indication signal (AIS) to the system while in loss of frame alignment state. -- Multiple loopback modes. -- Optional automatic line and payload loopback activate and deactivate modes. -- CEPT nailed-up connect loopback and CEPT nailed-up broadcast transmission TS-X in TS-0 transmit mode. -- Selectable test patterns for line transmission. -- Detection of framed and unframed pseudorandom and quasi-random test patterns. -- Programmable squelch and idle codes.
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Feature Descriptions
T1/E1 Framer Feature Descriptions
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Framing formats: -- Compliant with T1 standards ANSI T1.231 (1993), AT&T TR54016, AT&T TR62411 (1998). -- Unframed, transparent transmission in T1 and E1 formats. -- DS1 extended superframe (ESF). -- DS1 superframe (SF): D4; SLC-96; T1DM DDS; T1DM DDS with FDL access. -- DS1 independent transmit and receive framing modes when using the ESF and D4 formats. -- Compliant with ITU CEPT framing recommendation: 1. G.704 and G.706 basic frame format. 2. G.704 Section 2.3.3.4 and G.706 Section 4.2: CRC-4 multiframe search algorithm. 3. G.706 Annex B: CRC-4 multiframe search algorithm with 400 ms timer for interworking of CRC-4 and non-CRC-4 equipment. 4. G.706 Section 4.3.2 Note 2: monitoring of 915 CRC-4 checksum errors for loss of frame state. Framer line codes: -- DS1: alternate mark inversion (AMI); binary eight zero code suppression (B8ZS); per-channel zero code suppression; decoding bipolar violation monitor; monitoring of eight or fifteen bit intervals without positive or negative pulses error indication. -- DS1 independent transmit and receive path line code formats when using AMI/ZCS and B8ZS coding. -- ITU-CEPT: AMI; high-density bipolar 3 (HDB3) encoding and decoding bipolar violation monitoring, monitoring of four bit intervals without positive or negative pulses error indication. -- Single-rail option. Signaling: -- DS1: extended superframe 2-state, 4-state, and 16-state per-channel robbed bit. -- DS1: D4 superframe 2-state and 4-state perchannel robbed bit. -- DS1: SLC-96 superframe 2-state, 4-state, 9-state, and 16-state per-channel robbed bit. -- DS1: channel-24 message-oriented signaling. -- ITU CEPT: channel associated signaling (CAS). -- Transparent (all data channels). Alarm reporting, performance monitoring, and maintenance: -- ANSI T1.403-1995, AT&T TR 54016, and ITU G.826 standard error checking. -- Error and status counters: 1. Bipolar violations.
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System interface: -- Autonomous transmit and receive system interfaces. -- Independent transmit and receive frame synchronization input signals. -- Independent transmit and receive system interface clock. -- 2.048 Mbits/s, 2.048 MHz concentration highway interface (CHI) default mode. -- Optional 4.096 Mbits/s and 8.192 Mbits/s data rates. -- Optional 4.096 MHz and 8.192 MHz frequency system clock. -- Programmable clock edge for latching frame synchronization signals. -- Programmable clock edge for latching transmit and receive data. -- Programmable bit and byte offset. -- Programmable CHI master mode for the generation of the transmit CHI FS from internal logic with timing derived from the receive line clock signal. Digital phase comparator for clock generation in the receive and transmit paths. Lucent Technologies Inc. Lucent Technologies Inc.
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Functional Description
Note: The Concentration Highway Interface Specification, Lucent Technologies Microelectronics Group November 1990 (DS90-124SMOS) defines the transmit path as output to the system interface, and the receive path as input from the system interface. This document is consistent with that definition.
RPD[1--8] RND_RBPV[1--8] RLCK[1--8] RECEIVE CHANNEL [1--8] DECODER RECEIVE FRAMER UNIT RECEIVE ELASTIC STORE (2 FRAMES) TRANSMIT CONCENTRATION HIGHWAY INTERFACE (TCHI)
CHICK CHIFS TCHIDATA[1--8] TCHIDATAB[1--8] RFRMCK[1--8], RFRMDATA[1--8], RFS[1--8] RFDL[1--8], RFDLCK[1--8]
RECEIVE FACILITY DATA LINK MONITOR (HDLC OR TRANSPARENT FRAMING)
RECEIVE SIGNALING UNIT (DS1: ROBBED-BIT OR CEPT: TS16)
CHICK RLCK
RECEIVE CHANNEL DIGITAL PHASE DETECTOR
DIV-RLCK, DIV-CHICK, CHICK-EPLL
TRANSMIT CHANNEL [1--8]
TRANSMIT FACILITY DATA LINK MONITOR (HDLC OR TRANSPARENT FRAMING)
PLLCK[1--8] TRANSMIT SIGNALING UNIT (DS1: ROBBED-BIT OR CEPT: TS16) CHICK TRANSMIT CHANNEL DIGITAL PHASE DETECTOR
DIV-PLLCK, DIV-CHICK, PLLCK-EPLL TFDL[1--8], TFDLCK[1--8]
XMIT FRAMER TCLK SYNTHESIZER TND[1--8], TPD[1--8], TLCK[1--8] TRANSMIT FRAMER UNIT TRANSMIT ELASTIC STORE (2 FRAMES)
ENCODER
RECEIVE CONCENTRATION HIGHWAY INTERFACE (RCHI)
RCHIDATA_A[1--8] RCHIDATA_B[1--8] TFS[1--8] MPMODE
MICROPROCESSOR INTERFACE
A[11:0]
D[7:0]
CS
ALE_AS
RD_R/W
WR_DS
RDY_DTACK
INTERRUPT
MPCK 5-6937(F)r.4
Figure 1. TFRA08C13 Block Diagram (One of Eight Channels)
Lucent Technologies Inc. Lucent Technologies Inc.
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The default system interface is a 2.048 Mbits/s data and 2.048 MHz clock CHI serial bus. This CHI interface consists of independent transmit and receive paths. The CHI interface can be reconfigured into several modes: a 2.048 Mbits/s data interface and 4.096 MHz clock interface, a 4.096 Mbits/s data interface and 4.096 MHz clock interface, a 4.096 Mbits/s data interface and 8.192 MHz clock interface, a 8.192 Mbits/s data interface and 8.192 MHz clock interface, and 8.192 Mbits/s data interface. The signaling formats supported are T1 per-channel robbed-bit signaling (RBS), channel-24 message-oriented signaling (MOS), and ITU-CEPT-E1 channelassociated signaling (CAS). In the T1, RBS mode voice and data channels are programmable. The entire payload can be forced into a data-only (no signaling channels) mode, i.e., transparent mode by programming one control bit. Signaling access can be through the on-chip signaling registers or the system CHI port in the associated signaling mode. Data and its associated signaling information can be accessed through the CHI in either DS1 or CEPT-E1 modes. Extraction and insertion of the facility data link in ESF, T1DM, SLC-96, or CEPT-E1 modes are provided through a four-port serial interface or through a microprocessor-accessed, 64-byte FIFO either with HDLC formatting or transparently. In SLC-96 or CEPT-E1 frame formats, a facility data link (FDL) stack (registers in the framer section) is provided for FDL access. The bit-oriented ESF data-link messages defined in ANSI T1.403-1995 are monitored by the receive framer's facility data link unit. The transmit framer's facility data link unit overrides the XFDL-FIFO for the transmission of the bit-oriented ESF data-link messages defined in ANSI T1.403-1995. The receive framer includes a two-frame (64-bytes) elastic store buffer for jitter attenuation that performs controlled slips and provides an indication of slip direction. This buffer can be programmed to operate as a function of the receive line clock and can be reduced to one-frame (32-bytes) in length.
Functional Description (continued)
The Lucent Technologies Microelectronics Group TFRA08C13 OCTAL T1/E1 Framer provides eight complete T1/E1 interfaces each consisting of a fully integrated, full-featured, primary rate framer with an HDLC formatter for facility data link access. The TFRA08C13 provides glueless interconnection from a T1 or E1 analog line interface to devices interfacing to its CHI; for example, the Lucent T7270 Time-Slot Interchanger or T7115A Synchronous Protocol Data Formatter. The line codes supported in the framer unit include AMI, T1 B8ZS, per-channel T1 zero code suppression, and ITU-CEPT HDB3. The framer supports DS1 superframe (D4, T1DM, SLC-96) and extended superframe (ESF) formats. The framer also supports, ITU-CEPT-E1 basic frame, ITU-CEPT-E1 time slot 0 multiframe, and time slot 16 multiframe formats. The receive framer monitors the following alarms: loss of receive clock, loss of frame, alarm indication signal (AIS), remote frame alarms, and remote multiframe alarms. These alarms are detected as defined by the appropriate ANSI, AT&T, and ITU standards. It is recommended that the LIU/Framer interface be placed in dual rail mode, which allows the framers error/event detector to detect and report code and BPV errors. Performance monitoring as specified by AT&T, ANSI, and ITU is provided through counters monitoring bipolar violation, frame bit errors, CRC errors, errored events, errored seconds, bursty errored seconds, severely errored seconds, and unavailable seconds. In-band loopback activation and deactivation codes can be transmitted to the line via the payload or the facility data link. In-band loopback activation and deactivation codes in the payload or the facility data link are detected. System, payload, and line loopbacks are programmable.
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Functional Description (continued)
Accessing internal registers is done via the demultiplexed address and data bus microprocessor interface using either the Intel 80188 (or 80X88) interface protocol with independent read and write signals or the Motorola MC680X0 or M68360 interface protocol with address and data strobe signals. The TFRA08C13 is manufactured using low-power CMOS technology and is packaged in an 352-pin plastic ball grid array (PBGA) with 50 mils ball pitch.
RPD, RND_RBPV RLCK RECEIVE T1/E1 FRAME ALIGNMENT MONITOR, REALIGNER, AND SYNC GENERATOR: - SF: D4, SLC-96, DDS; - ESF - CEPT: BASIC FRAME, CRC-4 MULTIFRAME, & SIGNALING MULTIFRAME RECEIVE PERFORMANCE MONITOR: - BIPOLAR VIOLATION ERRORS - T1/E1 CRC ERRORS - ERRORED EVENTS - ERRORED SECONDS - BURSTY ERRORED SECONDS - SEVERELY ERRORED SECONDS - UNAVAILABLE SECONDS RECEIVE ALARM MONITOR: - ANALOG LOSS OF SIGNAL - DIGITAL LOSS OF SIGNAL - REMOTE FRAME ALARM - CEPT REMOTE MULTIFRAME ALARM - ALARM INDICATION SIGNAL (AIS) - SLIPS RECEIVE PATTERN MONITOR: - QUASI-RANDOM: 220 - 1 - PSEUDORANDOM: 215 - 1 - ANSI T1.403 BIT-ORIENTED AND ESF-FDL ACTIVATE AND DEACTIVATE LINE LOOPBACK CODES - CEPT AUXILIARY PATTERN (CEPT = 01) - CEPT ACTIVATE AND DEACTIVATE LOOPBACK CODES - CEPT Sa6 CODES RECEIVE FACILITY DATA LINK EXTRACTER AND MONITOR: - SLC-96 FORMAT - DDS ACCESS - ANSI T1.403-1989 ESF FORMAT: * BIT-ORIENTED MESSAGES * MESSAGE-ORIENTED MESSAGES RECEIVE FDL HDLC EXTRACTER: - 64-byte RECEIVE FIFO - TRANSPARENT MODE (NO HDLC FRAMING) - MICROPROCESSOR ACCESS RECEIVE ELASTIC STORE BUFFER (2 FRAMES) TRANSMIT CONCENTRATION HIGHWAY INTERFACE (RATE ADAPTER) CHIFS TCHIDATA/B
RFRMCK
RECEIVE SLIP MONITOR
INTERNAL SYSTEM CLOCK
CHICK
RECEIVE SIGNALING EXTRACTER: - DS1 ROBBED-BIT SIGNALING (RBS) - CEPT CHANNEL ASSOCIATED AND COMMON CHANNEL SIGNALING - CONCENTRATION HIGHWAY ACCESS - MICROPROCESSOR ACCESS
RFDLCK RFDL
5-6965(F)
Figure 2. TFRA08C13 Block Diagram: Receive Section (One of Eight Channels)
Lucent Technologies Inc. Lucent Technologies Inc.
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Preliminary Data Sheet October 2000
Functional Description (continued)
TLCK TND, TPD
LINE FORMAT ENCODER (AMI; B8ZS; HDB3)
TRANSMIT CRC GENERATOR: - ESF - CEPT
TRANSMIT T1/E1 FRAME FORMATTER, AND FRAME SYNC GENERATOR: - SF: D4, SLC-96, DDS; SIGNALING SUPERFRAME - ESF - CEPT: BASIC FRAME, CRC-4 MULTIFRAME, AND SIGNALING MULTIFRAME - TRANSPARENT FRAMING
TRANSMIT FACILITY DATA LINK INSERTER: - SLC-96 FORMAT - DDS ACCESS - ANSI T1.403-1989 ESF FORMAT: * BIT-ORIENTED MESSAGES * MESSAGE-ORIENTED MESSAGES TRANSMIT FDL HDLC INSERTER: - 64-byte TRANSMIT FIFO - TRANSPARENT MODE (NO HDLC FRAMING) - MICROPROCESSOR ACCESS
TFDL
TFDLCK
TRANSMIT PATTERN GENERATOR: - QUASI-RANDOM: 220 - 1 - PSEUDORANDOM: 215 - 1 - ANSI T1.403 BIT-ORIENTED AND ESF-FDL ACTIVATE AND DEACTIVATE LINE LOOPBACK CODES - CEPT AUXILIARY PATTERN (CEPT = 01) - CEPT ACTIVATE AND DEACTIVATE LOOPBACK CODES - CEPT Sa6 CODES
TRANSMIT SIGNALING INSERTER: - DS1 ROBBED-BIT SIGNALING (RBS) - CEPT CHANNEL ASSOCIATED AND COMMON-CHANNEL SIGNALING - CONCENTRATION HIGHWAY ACCESS - MICROPROCESSOR ACCESS
TRANSMIT ELASTIC STORE BUFFER (2 FRAMES)
RECEIVE CONCENTRATION HIGHWAY INTERFACE (RATE ADAPTER)
CHICK CHIFS RCHIDATA/B
TRANSMIT ALARM MONITOR: - LOSS OF SYSTEM BIFRAME ALIGNMENT - SYSTEM ALARM INDICATION SIGNAL (AIS)
5-6964(F)
Figure 3. TFRA08C13 Block Diagram: Transmit Section (One of Eight Channels)
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Pin Information
The package type and pin assignment for the TFRA08C13 is illustrated in Figure 4.
AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
TFRA08CF13 352-PIN PBGA
A1 BALL CORNER
5-6966(F)
Figure 4. Pin Assignment
Lucent Technologies Inc. Lucent Technologies Inc.
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Preliminary Data Sheet October 2000
Pin Information (continued)
Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 L1 L2 16 Signal Name NC NC NC RCHIDATAB1 RND8 NC RCHIDATA8 TSSFS8 TCHIDATAB8 RCRCMFS8 RFRMCK8 TPD8 VSSD VDDD NC NC NC VSS CHIFS PLLCK7 RCHIDATA7 TSSFS7 RFDL7 RSSFS7 RFRMDATA7 NC TFDLCK1 NC TFDL1 RPD1 RPD8 NC TFDLCK8 TFS8 RFDL8 RFS8 TND8 DS1/CEPT8 PLLCK2 RND2 Pin B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 R25 R26 Signal Name NC NC NC NC NC 3-STATE RND7 RCHIDATAB7 TCRCMFS7 TCHIDATA7 RCRCMFS7 RFS7 NC NC TSSFS1 TCRCMFS1 NC NC RCHIDATA1 RND1 VSS RCHIDATAB8 TCRCMFS8 TCHIDATA8 RSSFS8 TLCK8 RLCK8 NC NC NC VSSA NC RESET RPD7 TFDL7 TFS7 RFDLCK7 NC TND6 TLCK6 Pin C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E23 E24 E25 E26 F1 F2 Y23 Y24 Signal Name NC NC TCHIDATA1 TFS1 TCHIDATAB1 NC PLLCK1 NC PLLCK8 TFDL8 NC RFDLCK8 NC RFRMDATA8 NC NC NC NC VDDA CHICK NC TFDLCK7 NC TCHIDATAB7 NC RFRMCLK7 NC NC RSSFS1 RFDL1 RCRCMFS1 RFDLCK1 TLCK7 VDD TPD7 TND7 TLCK1 RFS1 TCHIDATAB5 TFDL5 Pin F3 F4 F23 F24 F25 F26 G1 G2 G3 G4 G23 G24 G25 G26 H1 H2 H3 H4 H23 H24 H25 H26 J1 J2 J3 J4 J23 J24 J25 J26 K1 K2 K3 K4 K23 K24 K25 K26 Signal Name RFRMCLK1 NC NC NC LOPLLCLK DS1/CEPT7 TPD1 TND1 VSS RFRMDATA1 LORLCK RLCK7 DIV-PLLCK PLLCK-EPLL NC RLCK1 TCK NC DIV-RLCK CHICK-EPLL RND6 DIV-CHICK TDI TRST VSS DS1/CEPT1 NC DIV-CHICK NC RPD6 TDO TMS RPD2 VDD PLLCK6 VSS VDD NC
AC19 TPD4 AC20 DS1/CEPT5 Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Pin Information (continued)
Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order (continued) Pin L3 L4 L23 L24 L25 L26 M1 M2 M3 M4 M23 M24 M25 M26 N1 N2 N3 N4 N23 N24 N25 N26 P1 P2 P3 P4 P23 P24 P25 P26 R1 R2 R3 R4 R23 R24 Signal Name RCHIDATA2 NC NC NC TFDLCK6 RCHIDATA6 RCHIDATAB2 VDD TSSFS2 TFDLCK2 RCHIDATAB6 TFDL6 TFS6 TCRCMFS6 TCRCMFS2 TFDL2 RFDL2 NC RFDL6 TSSFS6 RFDLCK6 TCHIDATA6 TCHIDATA2 TFS2 RCRCMFS2 TCHIDATAB2 NC TCHIDATAB6 RFRMDATA6 RSSFS6 RSSFS2 RFDLCK2 RFRMDATA2 TLCK2 RFS6 RCRCMFS6 Pin T1 T2 T3 T4 T23 T24 T25 T26 U1 U2 U3 U4 U23 U24 U25 U26 V1 V2 V3 V4 V23 V24 V25 V26 W1 W2 W3 W4 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Signal Name RFRMCLK2 RFS2 NC NC NC RFRMCLK6 DS1/CEPT6 TPD6 TPD2 TND2 VDD RLCK2 ALE_AS RLCK6 CS RD_RW DS1/CEPT2 NC PLLCK3 NC RCHIDATAB5 WR_DS RND5 RDY_DTACK RPD3 RND3 TFDL3 RCHIDATAB3 NC RPD5 RCHIDATA5 PLLCK5 RCHIDATA3 VSS TFS3 TCRCMFS3 Pin Y25 Y26 AA1 AA2 AA3 AA4 Signal Name TCRCMFS5 TFDLCK5 TSSFS3 TFDLCK3 RFDL3 NC Pin Signal Name
AC21 NC AC22 NC AC23 NC AC24 RFRMDATA5 AC25 RFRMCLK5 AC26 RFS5 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 NC RFRMDATA3 NC TPD3 A1 A4 A8 INTERRUPT RND4
AA23 NC AA24 TFS5 AA25 TCHIDATA5 AA26 TSSFS5 AB1 AB2 AB3 AB4 TCHIDATA3 TCHIDATAB3 RFS3 RCRCMFS3
AB23 RCRCMFS5 AB24 RFDLCK5 AB25 RSSFS5 AB26 RFDL5 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 RSSFS3 RFDLCK3 NC NC A0 NC A3 NC A10
AD10 RCHIDATA4 AD11 TSSFS4 AD12 AD0 AD13 AD4 AD14 NC AD15 NC AD16 RCRCMFS4 AD17 RFRMCLK4 AD18 VDD AD19 DS1/CEPT4 AD20 VSS AD21 NC AD22 NC AD23 NC AD24 NC AD25 NC AD26 VSS AE1 AE2 AE3 AE4 NC NC TLCK3 TND3
AC10 PLLCK4 AC11 NC AC12 TCHIDATAB4 AC13 NC AC14 AD2 AC15 RFDL4 AC16 NC AC17 RFS4 AC18 NC
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Pin Information (continued)
Table 1. Pin Assignments for 352-Pin PBGA by Pin Number Order (continued) Pin AE5 AE6 AE7 AE8 AE9 Signal Name DS1/CEPT3 A2 A6 A9 SECOND Pin Signal Name Pin AF3 AF4 AF5 AF6 AF7 AF8 AF9 Signal Name VDD RLCK3 VDD A5 A7 A11 MPMODE Pin Signal Name
AE17 RFDLCK4 AE18 RFRMDATA4 AE19 NC AE20 TND4 AE21 VSS AE22 TPD5 AE23 NC AE24 NC AE25 NC AE26 TLCK5 AF1 AF2 NC RFRMCLK3
AF15 AD6 AF16 NC AF17 RSSFS4 AF18 NC AF19 TLCK4 AF20 RLCK4 AF21 RLCK5 AF22 TND5 AF23 NC AF24 NC AF25 NC AF26 NC
AE10 MPCLK AE11 RCHIDATAB4 AE12 TFDLCK4 AE13 TFS4 AE14 AD1 AE15 AD5 AE16 AD7
AF10 RPD4 AF11 TFDL4 AF12 TCRCMFS4 AF13 TCHIDATA4 AF14 AD3
Table 2 shows the list of the TFRA08C13 pins and a functional description for each. Table 2. Pin Descriptions Pins AF3, AF5, AD18, K25, E24, K4, M2, U3 AD20, AD26, AE21, G3, K24, A18, J3, C7, Y2 D17 Symbol VDD Type* P Description 3.3 V Power Supply. 3.3 V 5%. Each of these pins must be bypassed with a 0.1 F capacitor to VSS, as close to the pin as possible.
VSS
G
Ground.
VDDA
P
3.3 V Quiet Analog Power Supply. This pin must be bypassed with a 0.1 F capacitor to VSSA, as close to the pin as possible. In addition, this pin should be isolated from the 3.3 V power plane with an inductive bead. 3.3 V Quiet Analog Ground. 3.3 V Quiet Digital Power Supply. This pin must be bypassed with a 0.1 F capacitor to VSSD, as close to the pin as possible. In addition, this pin should be isolated from the 3.3 V power plane with an inductive bead. 3.3 V Quiet Digital Ground. 3-State (Active-Low). Asserting this pin low forces the channel outputs into a high-impedance state. Reset (Active-Low). Asserting this pin low resets all channels on the entire device.
C17 A14
VSSA VDDD
G P
A13 B18 C19
*
VSSD 3-STATE RESET
G I
u
Iu
Iu indicates an internal pull-up, Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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TFRA08C13 OCTAL T1/E1 Framer
Pin Information (continued)
Table 2. Pin Descriptions (continued) Pins AE9 Symbol SECOND Type* O Description Second Pulse. A one second timer with an active-high pulse. The duration of the pulse is one RLCK cycle. Framer_1's receive line clock signal (RLCK1) is the default clock source for the internal second pulse timer. The internal second pulse is retimed in the individual framer sections with their corresponding receive line clock signal RLCK. When LORLCK_(N) is active, then Framer_(N + 1)'s receive line clock signal is used as the clock signal source for the internal second pulse timer. The second pulse is used for performance monitoring. CHI Clock. 2.048 MHz, 4.096 MHz, or 8.192 MHz. CHI Frame Sync. CHI 8 kHz input frame synchronization pulse. Pulse width must be a minimum of one clock period of CHICK and a maximum of a 50% duty cycle square wave. Error Phase-Lock Loop Signal. The error signal proportional to the phase difference between DIV-CHICK and DIV-RLCK as detected from the internal PLL circuitry (see Table 66. Global Control Register (GREG8) (008) Divided-Down PLLCK Clock. 32 kHz or 8 kHz clock signal derived from the PLLCK input signal (see Table 150. CHI Common Control Register (FRM_PR45) (Y8D)). Error Phase-Lock Loop Signal. The error signal proportional to the phase difference between DIV-PLLCK and DIV-CHICK as detected by the internal PLL circuitry (refer to the Phase-Lock Loop section). Divided-Down Receive Line Clock. 8 kHz clock signal derived from the recovered receive line interface unit clock or the RLCK input signal. The choice of which receive framer clock to use is defined in Table 66. Global Control Register (GREG8) (008). Divided-Down CHI Clock. 8 kHz clock signal derived from the transmit CHI CLOCK input signal (see Table 66. Global Control Register (GREG8) (008)). DS1/CEPT. Strap to VDD to enable DS1 operation in the framer unit. Strap to VSS to enable CEPT operation in the framer unit.
D18 A19
CHICK CHIFS
I I
H24
CHICK-EPLL
O
G25
DIV-PLLCK
O
G26
PLLCK-EPLL
O
H23
DIV-RLCK
O
H26, J24
DIV-CHICK
O
J4 V1 AE5 AD19 AC20 T25 F26 B12
u
DS1/CEPT[1] DS1/CEPT[2] DS1/CEPT[3] DS1/CEPT[4] DS1/CEPT[5] DS1/CEPT[6] DS1/CEPT[7] DS1/CEPT[8]
Iu
* I indicates an internal pull-up, Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Pin Information (continued)
Table 2. Pin Descriptions (continued) Pins D5 L1 V3 AC10 W26 K23 A20 D7 F25 Symbol PLLCK[1] PLLCK[2] PLLCK[3] PLLCK[4] PLLCK[5] PLLCK[6] PLLCK[7] PLLCK[8] LOPLLCK O Loss of PLLCK Clock. This pin is asserted high when the PLLCK clock does not toggle for a 250 s interval. This pin is deasserted 250 s after the first edge of PLLCK (see Table 66. Global Control Register (GREG8) (008)). Transmit Framer Line Interface Clock. Optional 1.544 MHz DS1 or 2.048 MHz output signal from the transmit framer. TND and TPD data changes on the rising edge of TLCK. Type* I Description Transmit Framer Phase-Locked Line Interface Clock. Clock signal used to time the transmit framer. This signal must be phase-locked to CHICK clock signal. In DS1 frame formats, PLLCK can be a lowfrequency signal (1.544 MHz) or a high frequency signal (6.176 MHz). In CEPT frame formats, PLLCK can be a low-frequency signal (2.048 MHz) or a high-frequency signal (8.192 MHz).
F1 R4 AE3 AF19 AE26 R26 E23 C12 G1 U1 AD4 AC19 AE22 T26 E25 A12 G2 U2 AE4 AE20 AF22 R25 E26 B11
u
TLCK[1] TLCK[2] TLCK[3] TLCK[4] TLCK[5] TLCK[6] TLCK[7] TLCK[8] TPD[1] TPD[2] TPD[3] TPD[4] TPD[5] TPD[6] TPD[7] TPD[8] TND[1] TND[2] TND[3] TND[4] TND[5] TND[6] TND[7] TND[8]
O
O
Transmit Line Interface Positive-Rail Data. This signal is the transmit framer positive NRZ output data. Data changes on the rising edge of TLCK. In the single-rail mode, TPD = transmit framer data.
O
Transmit Line Interface Negative-Rail Data. This signal is the transmit framer negative NRZ output data. Data changes on the rising edge of TLCK. In the single-rail mode, TND = 0.
* I indicates an internal pull-up, Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Pin Information (continued)
Table 2. Pin Descriptions (continued) Pins D2 P2 Y3 AE13 AA24 M25 C22 B8 B1 M4 AA2 AE12 Y26 L25 D20 B7 B3 N2 W3 AF11 Y24 M24 C21 D8 C5 L3 Y1 AD10 W25 L26 A21 A7
u
Symbol TFS[1] TFS[2] TFS[3] TFS[4] TFS[5] TFS[6] TFS[7] TFS[8] TFDLCK[1] TFDLCK[2] TFDLCK[3] TFDLCK[4] TFDLCK[5] TFDLCK[6] TFDLCK[7] TFDLCK[8] TFDL[1] TFDL[2] TFDL[3] TFDL[4] TFDL[5] TFDL[6] TFDL[7] TFDL[8] RCHIDATA[1] RCHIDATA[2] RCHIDATA[3] RCHIDATA[4] RCHIDATA[5] RCHIDATA[6] RCHIDATA[7] RCHIDATA[8]
Type* O
Description Transmit Framer Frame Sync. This signal is the 8 kHz frame synchronization pulse in the transmit framer. This signal is active-high.
O
Transmit Facility Data Link Clock. In DS1-DDS with data link access, this is an 8 kHz clock signal; otherwise, 4 kHz. The transmit frame latches data link bits on the falling edge of TFDLCK.
I
Transmit Facility Data Link. Optional serial input facility data link bit stream inserted into the transmit line data stream by the transmit framer. In DS1-DDS with data link access, this is an 8 kbits/s signal; otherwise, 4 kbits/s. In the CEPT frame format, TFDL can be programmed to one of the XSa bits of the NOT FAS frame time slot 0.
I
Receive CHI Data. Serial input system data at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s.
* I indicates an internal pull-up, Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Pin Information (continued)
Table 2. Pin Descriptions (continued) Pins A4 M1 W4 AE11 V23 M23 B20 C8 G23 Symbol RCHIDATAB[1] RCHIDATAB[2] RCHIDATAB[3] RCHIDATAB[4] RCHIDATAB[5] RCHIDATAB[6] RCHIDATAB[7] RCHIDATAB[8] LORLCK Type* I Description Receive CHI Data B. Serial input system data at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s.
O
Loss of Receive Clock. This pin is asserted high (logic 1) when RLCK in the receive framer does not toggle for a 250 s interval. Once asserted, this signal is deasserted on the first edge of RLCK (See Table 66. Global Control Register (GREG8) (008)). Receive Framer Line Interface Clock. This is the 1.544 MHz DS1 or 2.048 MHz input clock signal used by the receive framer to latch RPD and RND data.
H2 U4 AF4 AF20 AF21 U24 G24 C13 B4 K3 W1 AF10 W24 J26 C20 B5 C6 L2 W2 AD9 V25 H25 B19 A5
Iu
RLCK[1] RLCK[2] RLCK[3] RLCK[4] RLCK[5] RLCK[6] RLCK[7] RLCK[8] RPD[1] RPD[2] RPD[3] RPD[4] RPD[5] RPD[6] RPD[7] RP81] RND[1] RND[2] RND[3] RN[4] RND[5] RND[6] RND[7] RND[8]
I
I
Receive Positive-Rail Data. NRZ serial data latched by the rising edge of RLCK. Data rates: DS1-1.544 Mbits/s; CEPT-2.048 Mbits/s. Optional single-rail NRZ receive data latched by the rising edge of RLCK.
I
Receive Negative-Rail Data. Nonreturn-to-zero (NRZ) serial data latched by the rising edge of RLCK. Data rates: DS1-1.544 Mbits/s; CEPT-2.048 Mbits/s. In the single-rail mode, when RND = 1 the receive bipolar violation counter increments once for each rising edge of RLCK.
* indicates an internal pull-up, Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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TFRA08C13 OCTAL T1/E1 Framer
Pin Information (continued)
Table 2. Pin Descriptions (continued) Pins F3 T1 AF2 AD17 AC25 T24 D24 A11 G4 R3 AD2 AE18 AC24 P25 A25 D12 F2 T2 AB3 AC17 AC26 R23 B24 B10 E4 R2 AC2 AE17 AB24 N25 C23 D10
u
Symbol RFRMCK[1] RFRMCK[2] RFRMCK[3] RFRMCK[4] RFRMCK[5] RFRMCK[6] RFRMCK[7] RFRMCK[8] RFRMDATA[1] RFRMDATA[2] RFRMDATA[3] RFRMDATA[4] RFRMDATA[5] RFRMDATA[6] RFRMDATA[7] RFRMDATA[8] RFS[1] RFS[2] RFS[3] RFS[4] RFS[5] RFS[6] RFS[7] RFS[8] RFDLCK[1] RFDLCK[2] RFDLCK[3] RFDLCK[4] RFDLCK[5] RFDLCK[6] RFDLCK[7] RFDLCK[8]
Type* O
Description Receive Framer Clock. Output receive framer clock signal used to clock out the receive framer output signals. In normal operation, this is the recovered receive line clock signal.
O
Receive Framer Data. This signal is the decoded data input to the receive elastic store. During loss of frame alignment, this signal is forced to 1.
O
Receive Frame Sync. This active-high signal is the 8 kHz frame synchronization pulse generated by the receive framer. During loss of frame alignment and signaling superframe or multiframe alignment, this signal is forced to 0.
O
Receive Facility Data Link Clock. In DS1-DDS with data link access, this is an 8 kHz clock signal. Otherwise, this is a 4 kHz clock signal. The receive data link bit changes on the falling edge of RFDLCK.
* I indicates an internal pull-up, Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Pin Information (continued)
Table 2. Pin Descriptions (continued) Pins E2 N3 AA3 AC15 AB26 N23 A23 B9 D1 P1 AB1 AF13 AA25 N26 B22 C10 D3 P4 AB2 AC12 Y23 P24 D22 A9 E1 R1 AC1 AF17 AB25 P26 A24 C11
*
Symbol RFDL[1] RFDL[2] RFDL[3] RFDL[4] RFDL[5] RFDL[6] RFDL[7] RFDL[8] TCHIDATA[1] TCHIDATA[2] TCHIDATA[3] TCHIDATA[4] TCHIDATA[5] TCHIDATA[6] TCHIDATA[7] TCHIDATA[8] TCHIDATAB[1] TCHIDATAB[2] TCHIDATAB[3] TCHIDATAB[4] TCHIDATAB[5] TCHIDATAB[6] TCHIDATAB[7] TCHIDATAB[8] RSSFS[1] RSSFS[2] RSSFS[3] RSSFS[4] RSSFS[5] RSSFS[6] RSSFS[7] RSSFS[8]
Type* O
Description Receive Facility Data Link. Serial output facility data link bit stream extracted from the receive line data stream by the receive framer. In DS1-DDS with data link access, this is an 8 kbits/s signal; otherwise, 4 kbits/s. In the CEPT frame format, RFDL can be programmed to one of the RSa bits of the NOT FAS frame TS0. During loss of frame alignment, this signal is 1.
O
Transmit CHI Data. Serial output system data at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a high-impedance state for all inactive time slots.
O
Transmit CHI Data B. Serial output system data at 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. This port is forced into a high-impedance state for all inactive time slots.
O
Receive Framer Signaling Superframe Sync. This active-high signal is the CEPT signaling superframe (multiframe) synchronization pulse in the receive framer.
Iu indicates an internal pull-up, Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Pin Information (continued)
Table 2. Pin Descriptions (continued) E3 P3 AB4 AD16 AB23 R24 B23 A10 C1 M3 AA1 AD11 AA26 N24 A22 A8 C2 N1 Y4 AF12 Y25 M26 B21 C9 AF9 RCRCMFS[1] RCRCMFS[2] RCRCMFS[3] RCRCMFS[4] RCRCMFS[5] RCRCMFS[6] RCRCMFS[7] RCRCMFS[8] TSSFS[1] TSSFS[2] TSSFS[3] TSSFS[4] TSSFS[5] TSSFS[6] TSSFS[7] TSSFS[8] TCRCMFS[1] TCRCMFS[2] TCRCMFS[3] TCRCMFS[4] TCRCMFS[5] TCRCMFS[6] TCRCMFS[7] TCRCMFS[8] MPMODE Iu MPMODE. Strap to ground to enable the Motorola 68360 microprocessor protocol (MODE1). Strap to VDD to enable the Intel 80X86/88 microprocessor protocol (MODE3). Read (Active-Low). In the Intel interface mode, the TFRA08C13 drives the data bus with the contents of the addressed register while RD is low. Read/Write. In the Motorola interface mode, this signal is asserted high for read accesses; this pin is asserted low for write accesses. O Transmit Framer CRC-4 Multiframe Sync. This signal is the CEPT CRC-4 submultiframe synchronization pulse in the transmit framer. This signal is active-high. O Transmit Framer Signaling Superframe Sync. This signal is the CEPT signaling superframe (multiframe) synchronization pulse in the transmit framer. This signal is active-high. O Receive Framer CRC-4 Multiframe Sync. This active-high signal is the CEPT CRC-4 multiframe synchronization pulse in the receive framer.
U26
RD_R/W
I
*
Iu indicates an internal pull-up, Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Pin Information (continued)
Table 2. Pin Descriptions (continued) Pins V24 Symbol WR_DS Type* I Description Write (Active-Low). In the Intel mode, the value present on the data bus is latched into the addressed register on the positive edge of the signal applied to WR. Data Strobe (Active-Low). In the Motorola mode, when AS is low and R/W is low (write), the value present on the data bus is latched into the addressed register on the positive edge of the signal applied to DS; when AS is low and R/W is high (read), the TFRA08C13 drives the data bus with the contents of the addressed register while DS is low. Chip Select (Active-Low). In the Intel interface mode, this pin must be asserted low to initiate a read or write access and kept low for the duration of the access; asserting CS low forces RDY out of its high-impedance state into a 0 state. Address Strobe (Active-Low). In the Motorola interface mode, this pin must be asserted low to initiate a read or write access and kept low for the duration of the access. Microprocessor Data Bus. Bidirectional data bus used for read and write accesses. 3-stated output.
U25
CS
I
U23
ALE_AS
I
AD12 AE14 AC14 AF14 AD13 AE15 AF15 AE16 AC5 AD5 AE6 AC7 AD6 AF6 AE7 AF7 AD7 AE8 AC9 AF8
u
D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
I/O
I
Microprocessor Address Bus. Address bus used to access the internal registers.
* I indicates an internal pull-up, Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Pin Information (continued)
Table 2. Pin Descriptions (continued) Pins AD8 Symbol INTERRUPT Type* O Description Interrupt. INTERRUPT is asserted high/low indicating an internal interrupt condition/event has been generated. Interrupt events/conditions are maskable through the control registers. This output can be wiredOR or wired-AND to any other logic output (see Table 64Global Control Register (GREG4) (004)). Ready. In the Intel interface mode, this pin is asserted high to indicate the completion of a read or write access; this pin is forced into a highimpedance state while CS is high. Data Transfer Acknowledge (Active-Low). In the Motorola interface mode, DTACK is asserted low to indicate the completion of a read or write access; DTACK is 1 otherwise. Microprocessor Clock. Microprocessor clock used in the Intel mode to generate the READY signal. JTAG Data Output. Serial output data sampled on the falling edge of TCK from the boundary-scan test circuitry. JTAG Data Input. Serial input data sampled on the rising edge of TCK for the boundary-scan test circuitry. JTAG Clock Input. TCK provides the clock for the boundary-scan test logic. JTAG Mode Select (Active-High). The signal values received at TMS are sampled on the rising edge of TCK and decoded by the boundaryscan TAP controller to control boundary-scan test operations. JTAG Reset Input (Active-Low). Assert this pin low to asynchronously initialize/reset the boundary-scan test logic.
V26
RDY_DTACK
O
AE10 K1 J1 H3 K2
MPCK TDO TDI TCK TMS
Iu O Iu Iu Iu
J2
*
TRST
Id
Iu indicates an internal pull-up, Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Pin Information (continued)
Table 2. Pin Descriptions (continued) Pins A1, A2, A3, A6, A15, A16, A17, A26, B2, B6, B13, B14, B15, B16, B17, B25, B26, C3, C4, C14, C15, C16, C18, C24, C25, C26, D4, D6, D9, D11, D13, D14, D15, D16, D19, D21, D23 D25, D26, F4, F23, F24, H1, H4, J23, J25, K26, L4, L23, L24, N4, P23, T3, T4 T23, V2, V4, W23, AA4, AA23, AC3, AC4, AC6, AC8, AC11, AC13, AC16, AC18, AC21, AC22, AC23, AD1, AD3, AD14, AD15, AD21, AD22, AD23, AD24, AD25, AE1, AE2, AE19, AE23, AE24, AE25, AF1, AF16, AF18, AF23, AF24, AF25, AF26
*
Symbol NC
Type* -- No Connection.
Description
Iu indicates an internal pull-up, Id indicates an internal pull-down. After RESET is deasserted, the channel is in the default framing mode, as a function of the DS1/CEPT pin. Asserting this pin low will initially force RDY to a low state.
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
LIU-Framer Interface
LIU-Framer Physical Interface
The transmit framer-LIU interface for the TFRA08C13 consists of the TND, TPD, and TLCK pins. In normal operations, TND, TPD, and TLCK are driven from the transmit framer and are connected to an external transmit line interface. The receive framer-LIU interface for the TFRA08C13 consists of the RPD, RND, and RLCK internal signals. In normal operations, RND, RPD, and RLCK are sourced from an external receive line interface unit and are directly connected to the receive framer. Figure 5 illustrates the interfaces of the transmit and receive framer units.
TRANSMIT HDLC FACILITY DATA LINK INTERFACE TFDLCK TFDL
TTIP
TRING
EXTERNAL TRANSMIT LINE INTERFACE UNIT (XLIU)
TLCK TND TPD
RCHIDATA TRANSMIT FRAMER (XFRMR) RECEIVE CONCENTRATION HIGHWAY INTERFACE (RCHI) RCHIDATAB CHIFS CHICK
PLLCK
LINE INTERFACE
RECEIVE HDLC FACILITY DATA LINK INTERFACE
SYSTEM INTERFACE
RFDLCK RFDL
RTIP
RRING
EXTERNAL RLCK RECEIVE LINE RND INTERFACE RPD UNIT (RLIU)
RECEIVE FRAMER (RFRMR)
TRANSMIT CONCENTRATION HIGHWAY INTERFACE (XCHI)
TCHIDATA TCHIDATAB
RFRMCK
5-7169(F)
Figure 5. Block Diagram of Framer Line Interface
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
LIU-Framer Interface (continued)
Figure 6 shows the timing requirements for the transmit and receive framer interfaces in the LIU-bypass mode.
BIT 0 OF FRM_PR45 IS THE HFLF BIT t1 PLLCK t2r-f t3 t2f-r t1-DS1 t1-CEPT HFLF = 0 648 ns 488 ns HFLF = 1 162 ns 122 ns
t2r-f: t2f-r: PLLCK TO TLCK DELAY = 50 ns t3-DS1 = 648 ns t3-CEPT = 488 ns
TLCK t4 TND, TPD t5-DS1 = 648 ns t5-CEPT = 488 ns t4 = TLCK TO VALID TPD, TND = 30 ns
t5 RLCK
t6 = RPD, RND SETUP TO RISING RLCK = 40 ns t6 RND, RPD t8 RFRMCK
5-4558(F).dr.1
t7
t7 = RPD, RND HOLD FROM RISING RLCK = 40 ns
t8r-f: t8f-r: RLCK TO RFRMCK DELAY = 50 ns
Figure 6. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
LIU-Framer Interface (continued)
Line Encoding
Single Rail The default line code is single-rail mode and single-rail function of the framer specified by FRM_PR8 bit 7 = 1, bit 6 = 1, and bit 5 = 0. In this mode, the framer bipolar encoder/decoder is disabled and monitoring of received BPV errors is done with the use of the RND input. When RND = 1, the BPV counter increments by one on the rising edge of RLCK. The transmit framer transmits data via the TPD output pin while TND is forced to a 0 state. Dual Rail In dual-rail mode, the dual-rail function of the framer is selected through FRM_PR8 bits 5--7. Bipolar encoding/ decoding is enabled in the framer. Noncoded/decoded data is exchanged between the LIU and framer via the RPD, RND, RCLK, TPD, TND, and TCLK LIU-framer interface. DS1: Alternate Mark Inversion (AMI) The default line code used for T1 applications is alternate mark inversion (AMI). The coding scheme represents a 1 with a pulse or mark on the positive or negative rail and a 0 with no pulse on either rails. This scheme is shown in Table 3. Table 3. AMI Encoding Input Bit Stream AMI Data 1011 -0+- 0000 0000 0111 0+-+ 1010 -0+0
The T1 ones density rule states that: In every 24 bits of information to be transmitted, there must be at least three pulses, and no more than 15 zeros may be transmitted consecutively. Receive ones density is monitored by the receive line interface as per T1M1.3/93-005, ITU G.775, or TR-TSY000009. The receive framer indicates excessive zeros upon detecting any zero string length greater than 15 contiguous zeros (no pulses on either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar violations.
DS1: Zero Code Suppression (ZCS)
Zero code suppression is a technique known as pulse stuffing in which the seventh bit of each time slot is stuffed with a one. The line format (shown in Table 4) limits the data rate of each time slot from 64 kbits/s to 56 kbits/s. The default ZCS format stuffs the seventh bit of those ALL-ZERO time slots programmed for robbed-bit signaling (as defined in the signaling control registers with the F and G bits).
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
LIU-Framer Interface (continued)
The receive framer indicates a bipolar violation upon detecting a block of 15 consecutive 0s with no AMI encoding (no pulses on either RPD or RND). When an internal bipolar violation and a violation of 15 consecutive 0s occur simultaneously, only one violation is indicated. Table 4. DS1 ZCS Encoding Input Bit Stream ZCS Data (Framer Mode) Default ZCS 00000000 00000010 00000010 01010000 01010010 01010000 00000000 00000010 00000000 (data time slot remains clear) 00000000 00000010 00000010
DS1: Binary 8 Zero Code Suppression (B8ZS) Clear channel transmission can be accomplished using binary 8 zero code suppression (B8ZS). Eight consecutive 0s are replaced with the B8ZS code. This code consists of two bipolar violations in bit position 4 and 7 and valid bipolar marks in bit positions 5 and 8. The receiving end recognizes this code and replaces it with the original string of eight 0s. The receive framer indicates excessive zeros upon detecting a block of eight or more consecutive 0s. (no pulses on either RPD or RND). Both excessive zeros and coding violations are indicated as bipolar violations. Table 5 shows the encoding of a string of 0s using B8ZS. B8ZS is recommended when ESF format is used. V represents a violation of the bipolar rule and B represents an inserted pulse conforming to the AMI rule. Table 5. DS1 B8ZS Encoding Bit Positions Before B8ZS After B8ZS* 1 0 0 2 0 0 3 0 0 4 0 V 5 0 B 6 0 0 7 0 V 8 0 B -- 1 B -- 0 0 -- 1 B 1 0 0 2 0 0 3 0 0 4 0 V 5 0 B 6 0 0 7 0 V 8 0 B
* Bits 5--6 represent a bipolar violation pair. Bipolar violation with respect to the last previous 1 bit.
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TFRA08C13 OCTAL T1/E1 Framer
LIU-Framer Interface (continued)
CEPT: High-Density Bipolar of Order 3 (HDB3)
The line code used for CEPT is described in ITU Rec. G.703 Section 6.1 as high-density bipolar of order 3 (HDB3). HDB3 uses a substitution code that acts on strings of four zeros. The substitute HDB3 codes are 000V and B00V, where V represents a violation of the bipolar rule and B represents an inserted pulse conforming to the AMI rule defined in ITU Rec. G.701, item 9004. The choice of the B00V or 000V is made so that the number of B pulses between consecutive V pulses is odd. In other words, successive V pulses are of alternate polarity so that no direct current (dc) component is introduced. The substitute codes follow each other if the string of zeros continues. The choice of the first substitute code is arbitrary. A line code error consists of two pulses of the same polarity that is not defined as one of the two substitute codes. Excessive zeros consists of any zero string length greater than four contiguous zeros. Both excessive zeros and coding violations are indicated as bipolar violations. An example is shown in Table 6. Table 6. ITUHDB3 Coding Input Bit Stream HDB3-coded Data HDB3-coded Levels HDB3 with 5 Double BPVs 1011 1011 -0+- -0+- 0000 000V 000- -000 1-BPV 01 01 0+ 0+ 0000 000V 000+ +00+ 3-BPV 0000 B00V -00- 0-- - 5-BPV 0000 B00V +00+ +00+ 0000 B00V -00- -00-
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Preliminary Data Sheet October 2000
Frame Formats
The supported North American T1 framing formats are superframe (D4, SLC-96, and digital data service-DDS) and extended superframe (ESF). The device can be programmed to support the ITU-CEPT-E1 basic format with and without CRC-4 multiframe formatting. This section describes these framing formats.
T1 Framing Structures
T1 is a digital transmission system which multiplexes twenty-four 64 kbits/s time slots (DS0) onto a serial link. The T1 system is the lowest level of hierarchy on the North American T-carrier system, as shown in Figure 7 Table 7. T-Carrier Hierarchy T Carrier T1 T1-C T2 T3 T4 DS0 Channels 24 48 96 672 4032 Bit Rate (Mbits/s) 1.544 3.152 6.312 44.736 274.176 Digital Signal Level DS1 DS1C DS2 DS3 DS4
Frame, Superframe, and Extended Superframe Definitions Each time slot (DS0) is an assembly of 8 bits sampled every 125 s. The data rate is 64 kbits/s and the sample rate is 8 kHz. Time-division multiplexing 24 DS0 time slots together produces a 192-bit (24 DS0s) frame. A framing bit is added to the beginning of each frame to allow for detection of frame boundaries and the transport of additional maintenance information. This 193-bit frame, also referred to as a DS1 frame, is repeated every 125 s to yield the 1.544 Mbits/s T1 data rate.DS1 frames are bundled together to form superframes or extended superframes.
FRAME 1
FRAME 2
FRAME 3
FRAME 23
FRAME 24
24-FRAME EXTENDED SUPERFRAME ESF = 3.0 ms
FRAME 1
FRAME 2
FRAME 11
FRAME 12
12-FRAME SUPERFRAME SF = 1.5 ms
F BIT
TIME SLOT 1
TIME SLOT 2
TIME SLOT 24
193-bit FRAME DS1 = 125 s
1
2
3
4
5
6
7
8
8-bit TIME SLOT DS0 = 5.19 s
5-4559(F).br.1
Figure 7. T1 Frame Structure
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
Transparent Framing Format The transmit framer can be programmed to transparently transmit 193 bits of system data to the line. The system interface must be programmed such that the stuffed time slots are 1, 5, 9, 13, 17, 21, 25, and 29 (FRM_PR43 bits 2--0 must be set to 000) and either transparent framing mode 1 or transparent framing mode 2 is enabled (FRM_PR26 bit 3 or bit 4 must be set to 1). In transparent mode 1 or mode 2, the transmit framer extracts from the receive system data bit 8 of time slot 1 and inserts this bit into the framing bit position of the transmit line data. The other 7 bits of the receive system time slot 1 are ignored by the transmit framer. The receive framer will extract the F-bit (or 193rd bit) of the receive line data and insert it into bit 7 of time slot 1 of the system data; the other bits of time slot 1 are set to 0. Frame integrity is maintained in both the transmit and receive framer sections.
TIME SLOT 1 TIME SLOT 2
TIME SLOT 3
TIME SLOT 31 TIME SLOT 32
32 TIME-SLOT CHI FRAME
SYSTEM INTERFACE CONTROL REGISTER BITS[2:0] = 000.
(STUFF TIME SLOT) 0 0 0 0 0 0 0 F BIT SYSTEM FRAME SYNC MASK REGISTER FRM_PR26 BIT 3 OR BIT 4 = 1. FRAME INTEGRITY IS MAINTAINED WITH F BIT AND THE SYSTEM PAYLOAD. TRAMSMIT FRAMER'S 193-bit FRAME DS1 = 125 s
5-5989(F).b
F BIT TIME SLOT 1 TIME SLOT 2
TIME SLOT 24
Figure 8. T1 Transparent Frame Structure In transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. Other than bipolar violations and unframed AIS monitoring, there is no processing of the receive line data. The receive framer will insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data. In transparent framing mode 2, the receive framer functions normally on receive line data. All normal monitoring of receive line data is performed and data is passed to the transmit CHI as programmed. The receive framer will insert the extracted framing bit of the receive line data into bit 8 of time slot 1 of the transmit system data. The remaining bits in time slot 1 are set to 0.
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Preliminary Data Sheet October 2000
Frame Formats (continued)
D4 Frame Format D4 superframe format consists of 12 DS1 frames. Table 8 shows the structure of the D4 superframe. Table 8. D4 Superframe Format Frame Number1 Framing Bits Bit Terminal Number2 Frame FT 1 2 3 4 5 6
5
Bit Used in Each Time Slot Signal Frame FS -- 0 -- 0 -- 1 -- 1 -- 1 -- 0 Traffic (All Channels) 1--8 1--8 1--8 1--8 1--8 1--7 1--8 1--8 1--8 1--8 1--8 1--7 Remote Alarm3 2 2 2 2 2 2 2 2 2 2 2 2
Signaling Options 2-State 4-State
Signaling None4
0 193 386 579 772 965 1158 1351 1544 1737 1930 2123
1 -- 0 -- 1 -- 0 -- 1 -- 0 --
-- -- -- -- -- 8 -- -- -- -- -- 8
-- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- A -- -- -- -- -- A
-- -- -- -- -- A -- -- -- -- -- B
7 8 9 10 11 12
5
1. Frame 1 is transmitted first. 2. Following ANSI T1.403, the bits are numbered 0--2315. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and bit 1 of each DS0 is transmitted first. 3. The remote alarm forces bit 2 of each time slot to a 0-state when enabled. The Japanese remote alarm forces framing bit 12 (bit number 2123) to a 1-state when enabled. 4. Signaling option none uses bit 8 for traffic data. 5. Frames 6 and 12 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.
The receive framer uses both the FT and FS framing bits during its frame alignment procedure.
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TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
Digital Data Service (DDS) Frame Format The superframe format for DDS is the same as that given for D4. DDS is intended to be used for data-only traffic, and as such, the system should ensure that the framer is in the nonsignaling mode. DDS uses time slot 24 (FAS channel) to transmit the remote frame alarm and data link bits. The format for time slot 24 is shown in Table 9. The facility data link timing is shown in Figure 9 below. Table 9. DDS Channel-24 Format Time Slot 24 = 10111YD0 Y = (bit 6) Remote frame alarm: 1 = no alarm state; 0 = alarm state D = (bit 7) Data link bits (8 kbits/s)
t8 TFDLCK t8: TFDLCK CYCLE = 125 s (DDS) 250 s (ALL OTHER MODES) t9 t9
TFDL
t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns
t10
RFDLCK
t10: RFDLCK CYCLE = 125 s (DDS) 250 s (ALL OTHER MODES)
t11 RFDL
t11: RFDLCK TO RFDL DELAY = 40 ns
5-3910(F).cr.1
Figure 9. T7633 Facility Data Link Access Timing of the Transmit and Receive Framer Sections
SLC-96 Frame Format SLC-96 superframe format consists of 12 DS1 frames similar to D4. The FT pattern is exactly the same as D4. The FS pattern uses that same structure as D4 but also incorporates a 24-bit data link word as shown below.
SSLC-96 24-bit DATA LINK WORD
Fs =
. . . 000111000111D1DDDDDDDDDDDDDDDDDDDDDDD24000111000111DDD . . .
FRAME FRAME N N+1 FRAME N+2 FRAME N+3 FRAME N+4 FRAME N+5 FRAME FRAME FRAME N+6 N+7 N+8
FRAME N-1
SLC-96 36-FRAME D-bit SUPERFRAME INTERVAL (72 DS1 FRAMES)
5-6421(F)r.1 .
Figure 10. SLC-96 Frame Format Lucent Technologies Inc. Lucent Technologies Inc. 37
TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Frame Formats (continued)
External TFDL Source. Data may be inserted and extracted from the SLC-96 data link from either the external facility data link (TFDL) ports or the SLC-96 data stack. Source selection is controlled by FRM_PR21 bit 6 and FRM_PR29 bit 5--bit 7. The transmit framer synchronizes on TFDL = 000111000111 . . . and forces a superframe boundary based on this pattern. When sourcing an external bit stream, it is the system's responsibility to ensure that TFDL data contain the pattern of 000111000111 . . . . The D pattern sequence is shown in Table 10. Table 11 shows the encoding for the line switch field. Table 10. SLC-96 Data Link Block Format Data Link Block D1 (leftmost bit) D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 (rightmost bit) Bit Definition C1--concentrator bit C2--concentrator bit C3--concentrator bit C4--concentrator bit C5--concentrator bit C6--concentrator bit C7--concentrator bit C8--concentrator bit C9--concentrator bit C10--concentrator bit C11--concentrator bit Spoiler bit 1 Spoiler bit 2 Spoiler bit 3 M1--maintenance bit M2--maintenance bit M3--maintenance bit A1--alarm bit A2--alarm bit S1--line-switch bit S2--line-switch bit S3--line-switch bit S4--line-switch bit Spoiler bit 4 Bit Value 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 0 1 0 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 Defined in Table 11 Defined in Table 11 Defined in Table 11 Defined in Table 11 1
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
Table 11. SLC-96 Line Switch Message Codes S1 1 1 1 1 1 0 0 0 S2 1 1 1 1 0 1 1 0 S3 1 1 0 0 1 0 0 1 S4 1 0 1 0 0 1 0 0 Code Definition Idle Switch line A receive Switch line B transmit Switch line C transmit Switch line D transmit Switch line B transmit and receive Switch line B transmit and receive Switch line B transmit and receive
Internal SLC-96 Stack Source. Optionally, a SLC-96 FDL stack may be used to insert and correspondingly extract the FDL information in the SLC-96 frame format. The transmit SLC-96 FDL bits are sourced from the transmit framer SLC-96 FDL stack. The SLC-96 FDL stack (see FRM_PR31--FRM_PR35) consists of five 8-bit registers that contain the SLC-96 FS and D-bit information as shown in Table 12. The transmit stack data is transmitted to the line when the stack enable mode is active in the parameter registers FRM_PR21 bit 6 = 1 and FRM_PR29 bit 5--bit 7 = x10 (binary). The receive SLC-96 stack data is received when the receive framer is in the superframe alignment state. In the SLC-96 mode, while in the loss of superframe alignment (LSFA) state, updating of the receive framer SLC-96 stack is halted and neither the receive stack interrupt nor receive stack flag are asserted. Table 12. Transmit and Receive SLC-96 Stack Structure Register Number Bit 7 (MSB) 1 (LSR) 2 3 4 5 0 0 C1 C9 M3 Bit 6 0 0 C2 C10 A1 Bit 5 0 0 C3 C11 A2 Bit 4 Bit 3 Bit 2 Bit 1 1 1 C7 M1 S4 Bit 0 (LSB) 1 1 C8 M2 SPB4 = 1
0 0 1 0 0 1 C4 C5 C6 SPB1 = 0 SPB2 = 1 SPB3 = 0 S1 S2 S3
Bit 5--bit 0 of the first 2 bytes of the SLC-96 FDL stack in Table 12 are transmitted to the line as the SLC-96 FS sequence. Bit 7 of the third stack register is transmitted as the C1 bit of the SLC-96 D sequence. The spoiler bits (SPB1, SPB2, SPB3, and SPB4) are taken directly from the transmit stack. The protocol for accessing the SLC-96 stack information for the transmit and receive framer is described below. The transmit SLC-96 stack must be written with valid data when transmitting stack data. The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 5 (SLC-96 transmit FDL stack ready) high. At this time, the system has about 9 ms to update the stack. Data written to the stack during this interval will be transmitted during the next SLC-96 superframe D-bit interval. By reading bit 5 in register SR4, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the transmit stack is not updated, then the content of the stack is retransmitted to the line. The start of the SLC-96 36-frame FS interval of the transmit framer is a function of the first 2 bytes of the SLC-96 transmit stack registers. These bytes must be programmed as shown in Table 12. Programming any other state into these two registers disables the proper transmission of the SLC-96 D bits. Once programmed correctly, the transmit SLC-96 D-bit stack is transmitted synchronous to the transmit SLC-96 superframe structure. On the receive side, the device indicates that it has received data in the receive FDL stack (registers FRM_SR54-- FRM_SR58) by setting bit 4 in register FRM_SR4 (SLC-96 receive FDL stack ready) high. The system then has about 9 ms to read the content of the stack before it is updated again (old data lost). By reading bit 4 in register FRM_SR4, the system clears this bit so that it can indicate the next time the receive stack is ready. As explained above, the SLC-96 receive stack is not updated when superframe alignment is lost. Lucent Technologies Inc. 39 Lucent Technologies Inc.
TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Frame Formats (continued)
Extended Superframe Format The extended superframe format consists of 24 DS1 frames. The F bits are used for frame alignment, superframe alignment, error checking, and facility data link transport. Table 13 shows the ESF frame format. Table 13. Extended Superframe (ESF) Structure
Frame Number1 Bit Number3 1 2 3 4 5 66 7 8 9 10 11 126 13 14 15 16 17 186 19 20 21 22 23 246 0 193 386 579 772 965 1158 1351 1544 1737 1930 2123 2316 2509 2702 2895 3088 3281 3474 3667 3860 4053 4246 4439 Frame Bit FE -- -- -- 0 -- -- -- 0 -- -- -- 1 -- -- -- 0 -- -- -- 1 -- -- -- 1 DL D -- D -- D -- D -- D -- D -- D -- D -- D -- D -- D -- D -- CRC-64 -- C1 -- -- -- C2 -- -- -- C3 -- -- -- C4 -- -- -- C5 -- -- -- C6 -- -- Bit Use in Each Time Slot Traffic 1--8 1--8 1--8 1--8 1--8 1--7 1--8 1--8 1--8 1--8 1--8 1--7 1--8 1--8 1--8 1--8 1--8 1--7 1--8 1--8 1--8 1--8 1--8 1--7 Signaling None5 -- -- -- -- -- 8 -- -- -- -- -- 8 -- -- -- -- -- 8 -- -- -- -- -- 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Signaling Option2 2-State -- -- -- -- -- A -- -- -- -- -- A -- -- -- -- -- A -- -- -- -- -- A 4-State -- -- -- -- -- A -- -- -- -- -- B -- -- -- -- -- A -- -- -- -- -- B 16-State -- -- -- -- -- A -- -- -- -- -- B -- -- -- -- -- C -- -- -- -- -- D
1. Frame 1 is transmitted first. 2. The remote alarm is a repeated 1111111100000000 pattern in the DL when enabled. 3. Following ANSI T1.403, the bits are numbered 0--4361. Bit 0 is transmitted first. Bits in each DS0 time slot are numbered 1 through 8, and bit 1 of each DS0 is transmitted first. 4. The C1 to C6 bits are the cyclic redundancy check-6 (CRC-6) checksum bits calculated over the previous extended superframe. 5. Signaling option none uses bit 8 for traffic data. 6. Frames 6, 12, 18, and 24 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled.
The ESF format allows for in-service error detection and diagnostics on T1 circuits. ESF format consist of 24 framing bits: 6 for framing synchronization (2 kbits/s); 6 for error detection (2 kbits/s); and 12 for in-service monitoring and diagnostics (4 kbits/s).
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
Cyclic redundancy checking is performed over the entire ESF data payload (4,608 data bits, with all 24 framing bits (FE, DL, CRC-6) set to 1 during calculations). The CRC-6 bits transmitted in ESF will be determined as follows:
s
The check bits, c1 through c6, contained in ESF(n + 1) will always be those associated with the contents of ESF(n), the immediately preceding ESF. When there is no ESF immediately preceding, the check bits may be assigned any value. For the purpose of CRC-6 calculation only, every F bit in ESF(n) is set to 1. ESF(n) is altered in no other way. The resulting 4632 bits of ESF(n) are used, in order of occurrence, to construct a polynomial in x such that the first bit of ESF(n) is the coefficient of the term x4631 and the last bit of ESF(n) is the coefficient of the term x0. The polynomial is multiplied by the factor x6, and the result is divided, modulo 2, by the generator polynomial x6 + x + 1. The coefficients of the remainder polynomial are used, in order of occurrence, as the ordered set of check bits, c1 through c6, that are transmitted in ESF(n + 1). The ordering is such that the coefficient of the term x5 in the remainder polynomial is check bit c1 and the coefficient of the term x0 in the remainder polynomial is check bit c6.
s s
s
The ESF remote frame alarm consists of a repeated eight ones followed by eight 0s transmitted in the data link position of the framing bits.
T1 Loss of Frame Alignment (LFA)
Loss of frame alignment condition for the superframe or the extended superframe formats is caused by the inability of the receive framer to maintain the proper sequence of frame bits. The number of errored framing bits required to detect a loss of frame alignment is given is Table 14. Table 14. T1 Loss of Frame Alignment Criteria Format D4 Number of Errored Framing Bits That Will Cause a Loss of Frame Alignment Condition 2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0. 2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0. 3 errored frame bits (FT or FS) or channel 24 FAS pattern out of 12 consecutive frame bits. 2 errored FE bits out of 4 consecutive FE bits or optionally 320 or more CRC-6 errored checksums within a one second interval if loss of frame alignment due to excessive CRC-6 errors is enabled in FRM_PR9.
SLC-96
DDS: Frame ESF
The receive framer indicates the loss of frame and superframe conditions by setting the LFA and LSFA bits (FRM_SR1 bit 0 and bit 1), respectively, in the status registers for the duration of the conditions. The local system may give indication of its LFA state to the remote end by transmitting a remote frame alarm (RFA). In addition, in the LFA state, the system may transmit an alarm indication signal (AIS) to the system interface.
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Frame Formats (continued)
T1 Frame Recovery Alignment Algorithms
When in a loss of frame alignment state, the receive framer searches for a new frame alignment and forces its internal circuitry to this new alignment. The receive framer's synchronization circuit inhibits realignment in T1 framing formats when repetitive data patterns emulate the T1 frame alignment patterns. T1 frame synchronization will not occur until all frame sequence emulating patterns disappear and only one valid pattern exists. The loss of frame alignment state will always force a loss of superframe alignment state. Superframe alignment is established only after frame alignment has been determined in the D4 and SLC-96 frame format. Table 15 gives the requirements for establishing T1 frame and superframe alignment. Table 15. T1 Frame Alignment Procedures Frame Format D4: Frame Alignment Procedure Using the FT frame position as the starting point, frame alignment is established when 24 consecutive FT and FS frame bits, excluding the twelfth FS bit, (48 total frames) are received error-free. Once frame alignment is established, then superframe alignment is determined. After frame alignment is determined, two valid superframe bit sequences using the FS bits must be received error-free to establish superframe alignment. Using the FT frame position as the starting point, frame alignment is established when 24 consecutive FT frame bits (48 total frames) are received error-free. Once frame alignment is established, then superframe alignment is determined. After frame alignment is determined, superframe alignment is established on the first valid superframe bit sequence 000111000111. Using the FT frame position as the starting point, frame alignment is established when six consecutive FT/FS frame bits and the DDS FAS in time slot 24 are received error-free. In the DDS format, there is no search for a superframe structure. Frame and superframe alignment is established simultaneously using the FE framing bit. Alignment is established when 24 consecutive FE bits are received error-free. Once frame/ superframe alignment is established, the CRC-6 receive monitor is enabled.
D4: Superframe
SLC-96: Frame
SLC-96: Superframe DDS: Frame
ESF
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
T1 Robbed-Bit Signaling
To enable signaling, register FRM_PR44 bit 0 (TSIG) must be set to 0. Robbed-bit signaling, used in either ESF or SF framing formats, robs the eighth bit of the voice channels of every sixth frame. The signaling bits are designated A, B, C, and D, depending on the signaling format used. The robbedbit signaling format used is defined by the state of the F and G bits in the signaling registers (see DS1: Robbed-Bit Signaling on page 61). The received channel robbed-bit signaling format is defined by the corresponding transmit signaling F and G bits. Table 16 shows the state of the transmitted signaling bits as a function of the F and G bits. Table 16. Robbed-Bit Signaling Options G 0 0 1 1 F 0 1 0 1 Robbed-Bit Signaling Format 6 ESF: 16-State SLC *: 9-State, 16-State 4-State Data channel (no signaling) 2-State A A Frame 12 B 18 C 24 D
B A B PAYLOAD DATA A A A A
* See register FRM_PR43 bit 3 and bit 4.
The robbed-bit signaling format for each of the 24 T1 transmit channels is programmed on a per-channel basis by setting the F and G bits in the transmit signaling direction.
SLC-96 9-State Signaling SLC-96 9-state signaling state is enabled by setting both the F and G bits in the signaling registers to the 0-state, setting the SLC-96 signaling control register FRM_PR43 bit 3 to 1, and setting register FRM_PR44 bit 0 to 0. Table 17 shows the state of the transmitted signaling bits to the line as a function of the A-, B-, C-, and D-bit settings in the transmit signaling registers. In Table 17 below, X indicates either a 1- or a 0-state, and T indicates a toggle, transition from either 0 to 1 or 1 to 0, of the transmitted signaling bit.
In the line receive direction, this signaling mode functions identically to the preceding transmit path description. Table 17. SLC-96 9-State Signaling Format Transmit Signaling Register Settings Transmit to the Line Signal Bits C 0 0 0 1 1 1 X X X D 0 1 X 0 1 X 0 1 X A = f(A, C) 0 0 0 T T T 1 1 1 B = f(B, D) 0 T 1 0 T 1 0 T 1
SLC-96 Signaling States
State 1 State 2 State 3 State 4 State 5 State 6 State 7 State 8 State 9
A 0 0 0 0 0 0 1 1 1
B 0 0 1 0 0 1 0 0 1
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Frame Formats (continued)
16-State Signaling The default signaling mode while in SLC-96 framing is 16-state signaling. SLC-96 16-state signaling is enabled by setting both the F and G bits in the signaling registers to the 0 state, setting the SLC-96 signaling control register FRM_PR43 bit 3 and bit 4 to 0, and setting register FRM_PR44 bit 0 to 0. Table 18 shows the state of the transmitted signaling bits to the line as a function of the A-, B-, C-, and D-bit settings in the transmit signaling registers. In Table 18 below, under Transmit to the Line Signal Bits, A and B are transmitted into one SLC-96 12-frame signaling superframe, while A' and B' are transmitted into the next successive SLC-96 12-frame signaling superframe. In the line receive direction, this signaling mode functions identically to the preceding transmit path description. The signaling mapping of this 16-state signaling mode is equivalent to the mapping of the SLC-96 9-state signaling mode. Table 18. 16-State Signaling Format Transmit Signaling Register Settings Transmit to the Line Signal Bits D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A' 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B' 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
SLC-96 Signaling States
State 0 State 1 State 2 State 3 State 4 State 5 State 6 State 7 State 8 State 9 State 10 State 11 State 12 State 13 State 14 State 15
A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
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TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
CEPT 2.048 Basic Frame, CRC-4 Time Slot 0, and Signaling Time Slot 16 Multiframe Structures
As defined in TU Rec. G.704, the CEPT 2.048 frame, CRC-4 multiframe, and channel associated signaling multiframe structures are illustrated in Figure 11
CRC-4 MULTIFRAME IN TIME SLOT 0 FRAME 0 OF CRC-4 MULTIFRAME
0000
X0 YM X1 X2
A1 B1 C1 D1 A16 B16 C16 D16 C1 0 01 C2 0 01 C3 0 11 C4 0 01 C1 0 11 C2 0 11 C3 0 E1 C4 0 E1 0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 11011 SA4 SA5 SA6 SA7 SA8 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 1 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 TIME SLOT 31 A2 B2 C2 D2 A17 B17 C17 D17 A3 B3 C3 D3 A18 B18 C18 D18 A4 B4 C4 D4 A19 B19 C19 D19 A5 B5 C5 D5 A20 B20 C20 D20 A6 B6 C6 D6 A21 B21 C21 D21 A7 B7 C7 D7 A22 B22 C22 D22 A8 B8 C8 D8 A23 B23 C23 D23 A9 B9 C9 D9 A24 B24 C24 D24 A10 B10 C10 D10 A25 B25 C25 D25 A11 B11 C11 D11 A26 B26 C26 D26 A12 B12 C12 D12 A27 B27 C27 D27 A13 B13 C13 D13 A28 B28 C28 D28 FRAME 15 OF CRC-4 MULTIFRAME A14 B14 C14 D14 A29 B29 C29 D29 A15 B15 C15 D15 A30 B30 C30 D30 CHANNEL ASSOCIATED SIGNALING MULTIFRAME IN TIME SLOT 16
FRAME 0 TIME SLOT 16 MULTIFRAME
FRAME 15 TIME SLOT 16 MULTIFRAME
CHANNEL NUMBERS REFER TO TELEPHONE CHANNEL NUMBERS. TIME SLOTS 1 TO 15 AND 17 TO 31 ARE ASSIGNED TO TELEPHONE CHANNELS NUMBERED FROM 1 TO 30.
Si 0 0
1
1
0
1
1
TIME SLOT 1
TIME SLOT 31
FAS FRAME PRIMARY BASIC FRAME STRUCTURE
Si 1 A SA4 SA5 SA6 SA7 SA8
TIME SLOT 1
TIME SLOT 31
NOT FAS FRAME
TIME SLOT 0
TIME SLOT 1
TIME SLOT 16
TIME SLOT 31
256-bit FRAME = 125 s
12
34
56
78
8-bit TIME SLOT = 3.90625 s
5-4548(F).cr.1
Figure 11. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe Structures
Lucent Technologies Inc. Lucent Technologies Inc.
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Preliminary Data Sheet October 2000
Frame Formats (continued)
CEPT 2.048 Basic Frame Structure
The ITU Rec. G.704 Section 2.3.1 defined frame length is 256 bits, numbered 1 to 256. The frame repetition rate is 8 kHz. The allocation of bits numbered 1 to 8 of the frame is shown in Table 19. Table 19. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame Basic Frames Frame Alignment Signal (FAS) Not Frame Alignment Signal (NOT FAS) Bit 1 (MSB) Si Si Bit 2 0 1 Bit 3 0 A Bit 4 1 Sa4 Bit 5 1 Sa5 Bit 6 0 Sa6 Bit 7 1 Sa7 Bit 8 (LSB) 1 Sa8
The function of each bit in Table 19 is described below:
s
The Si bits are reserved for international use. A specific use for these bits is described in Table 20. ITU CRC-4 Multiframe Structure. If no use is realized, these bits should be fixed at 1 on digital paths crossing an international border. Bit 2 of the NOT FAS frames is fixed to 1 to assist in avoiding simulations of the frame alignment signal. Bit 3 of the NOT FAS is the remote alarm indication (A bit). In undisturbed operation, this bit is set to 0; in alarm condition, set to 1. Bits 4--8 of the NOT FAS (Sa4--Sa8) may be recommended by ITU for use in specific point-to-point applications. Bit Sa4 may be used as a message-based data link for operations, maintenance, and performance monitoring. If the data link is accessed at intermediate points with consequent alterations to the Sa4 bit, the CRC-4 bits must be updated to retain the correct end-to-end path termination functions associated with the CRC-4 procedure. The receive framer does not implement the CRC-4 modifying algorithm described in ITU Rec. G.706 Annex C. Bits Sa4--Sa8, where these are not used, should be set to 1 on links crossing an international border. MSB = most significant bit and is transmitted first. LSB = least significant bit and is transmitted last.
s s
s
s s
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
Transparent Framing Format The transmit framer can be programmed to transparently transmit 256 bits of system data to the line. The transmit framer must be programmed to either transparent framing mode 1 or transparent framing mode 2 (see Table 136. Framer Reset and Transparent Mode Control Register (FRM_PR26) (Y7A)). In transparent mode 1 or mode 2, the transmit framer transmits all 256 bits of the RCHI payload unmodified to the line. Time slot 1 of the RCHI, determined by the CHIFS signal, is inserted into the FAS/NOT FAS time slot of the transmit line interface. Frame integrity is maintained in both the transmit and receive framer sections.
TIME SLOT 1 TIME SLOT 2
TIME SLOT 3
TIME SLOT 31 TIME SLOT 32
32 TIME-SLOT CHI FRAME
TIME SLOT 1 TIME SLOT 2
TIME SLOT 3
TIME SLOT 31 TIME SLOT 32
32 TIME-SLOT LINE FRAME
5-5988(F)
Figure 12. CEPT Transparent Frame Structure In transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. Other than bipolar violations and unframed AIS monitoring, there is no processing of the receive line data. The entire receive line payload is transmitted unmodified to the CHI. In transparent framing mode 2, the receive framer functions normally on the receive line data. All normal monitoring of receive line data is performed and data is transmitted to the CHI as programmed.
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
s
Frame Formats (continued)
CEPT Loss of Basic Frame Alignment (LFA)
Frame alignment is assumed to be lost when the following occurs :
s
If CRC-4 is enabled, loss of CRC-4 multiframe alignment is forced. If CRC-4 is enabled, the monitoring and processing of CRC-4 checksum errors is halted. If CRC-4 is enabled, all monitoring and processing of received E-bit information is halted. If CRC-4 is enabled, the receive continuous E-bit alarm is deactivated. If CRC-4 is enabled, optionally, E bit = 0 is transmitted to the line for the duration of loss of CRC-4 multiframe alignment if register FRM_PR28 bit 4 is set to 1. If time slot 16 signaling is enabled, loss of the signaling multiframe alignment is forced. If time slot 16 signaling is enabled, updating of the signaling data is halted.
s
s
As described in ITU Rec. G.706 Section 4.1.1, three consecutive incorrect frame alignment signals have been received. So as to limit the effect of spurious frame alignment signals, when bit 2 in time slot 0 in NOT FAS frames has been received with an error on three consecutive occasions. Optionally, as described in ITU Rec. G.706 Section 4.3.2, by exceeding a count of >914 errored CRC-4 blocks out of 1000, with the understanding that a count of 915 errored CRC blocks indicates false frame alignment. On demand via the control registers. In the LFA state: No additional FAS or NOT FAS errors are processed. The received remote frame alarm (received A bit) is deactivated. All NOT FAS bit (Si bit, A bit, and Sa4 to Sa8 bits) processing is halted. Receive Sa6 status bits are set to 0.
s
s
s
s
s
s
s s s s
CEPT Loss of Frame Alignment Recovery Algorithm
The receive framer begins the search for basic frame alignment one bit position beyond the position where the LFA state was detected. As defined in ITU Rec. G.706.4.1.2, frame alignment will be assumed to have been recovered when the following sequence is detected as follows:
s
s
s s s
Receive Sa6 code monitoring and counting is halted. All receive Sa stack data updates are halted. The receive Sa stack ready, register FRM_SR4 bit 6 and bit 7, is set to 0. If enabled, the receive Sa stack interrupt bit is set to 0. Receive data link (RFDL) is set to 1 and RFDCLK maintains previous alignment. Optionally, the remote alarm indication (A = 1) may be automatically transmitted to the line if register FRM_PR27 bit 0 is set to 1. Optionally, the alarm indication signal (AIS) may be automatically transmitted to the system if register FRM_PR19 bit 0 is set to 1.
s
For the first time, the presence of the correct frame alignment signal in frame n. The absence of the frame alignment signal in the following frame detected by verifying that bit 2 of the basic frame is a 1 in frame n + 1. For the second time, the presence of the correct frame alignment in the next frame, n + 2.
s s
s
Failure to meet the second or third bullet above will ini tiate a new basic frame search in frame n + 2.
s
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
CEPT Time Slot 0 CRC-4 Multiframe Structure
The CRC-4 multiframe is in bit 1 of each NOT FAS frame. As described in ITU Rec. G.704 Section 2.3.3.1, where there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability, then bit 1 of each frame may be used for a cyclic redundancy check-4 (CRC-4) procedure as detailed below. The allocation of bits 1--8 of time slot 0 of every frame is shown in Table 20 for the complete CRC-4 multiframe. Table 20. ITU CRC-4 Multiframe Structure Multiframe Submultiframe (SMF) I Frame Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bits 1 C1 0 C2 0 C3 1 C4 0 C1 1 C2 1 C3 E C4 E 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A 4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8
II
Notes: C1 to C4 = cyclic redundancy check-4 (CRC-4) bits. E = CRC-4 error indication bits. Sa4 to Sa8 = spare bits. A = remote frame alarm (RFA) bit (active-high); referred to as the A bit.
The CRC-4 multiframe consists of 16 frames numbered 0 to 15 and is divided into two eight-frame submultiframes (SMF), designated SMF-I and SMF-II that signifies their respective order of occurrence within the CRC-4 multiframe structure. The SMF is the CRC-4 block size (2048 bits). In those frames containing the frame alignment signal (FAS), bit 1 is used to transmit the CRC-4 bits. There are four CRC-4 bits, designated C1, C2, C3, and C4 in each SMF. In those frames not containing the frame alignment signal (NOT FAS), bit 1 is used to transmit the 6-bit CRC-4 multiframe alignment signal and two CRC-4 error indication bits (E). The multiframe alignment signal is defined in ITU Rec. G.704 Section 2.3.3.4, as 001011. Transmitted E bits should be set to 0 until both basic frame and CRC-4 multiframe alignment are established. Thereafter, the E bits should be used to indicate received errored submultiframes by setting the binary state of one E bit from 1 to 0 for each errored submultiframe. The received E bits will always be taken into account, by the receive E-bit processor*, even when the SMF that contains them is found to be errored. In the case where there exists equipment that does not use the E bits, the state of the E bits should be set to a binary 1 state.
* The receive E-bit processor will halt the monitoring of the received E bit during the loss of CRC-4 multiframe alignment.
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
CEPT Loss of CRC-4 Multiframe Alignment (LTS0MFA)
Loss of basic frame alignment forces the receive framer into a loss of CRC-4 multiframe alignment state. This state is reported by way of the status registers FRM_SR1 bit 2. Once basic frame alignment is achieved, a new search for CRC-4 multiframe alignment is initiated. During a loss of CRC-4 multiframe alignment state the following occurs:
s s
Frame Formats (continued)
The CRC-4 word, located in submultiframe N, is the remainder after multiplication by x4 and then division (modulo 2) by the generator polynomial x4 + x + 1, of the polynomial representation of the submultiframe N - 1. Representing the contents of the submultiframe check block as a polynomial, the first bit in the block, i.e., frame 0, bit 1 or frame 8, bit 1, is taken as being the most significant bit and the least significant bit in the check block is frame 7 or frame 15, bit 256. Similarly, C1 is defined to be the most significant bit of the remainder and C4 the least significant bit of the remainder. The encoding procedure, as described in ITU Rec. G.704 Section 2.3.3.5.2, follows:
s
The CRC-4 error counter is halted. The CRC-4 error monitoring circuit for errored seconds and severely errored seconds is halted. The received E-bit counter is halted. The received E-bit monitoring circuit for errored seconds and severely errored seconds at the remote end interface is halted. Receive continuous E-bit monitoring is halted. All receive Sa6 code monitoring and counting functions are halted. The updating of the receive Sa stack is halted and the receive Sa stack interrupt is deactivated. Optionally, A = 1 may be automatically transmitted to the line if register FRM_PR27 bit 2 is set to 1. Optionally, E = 0 may be automatically transmitted to the line if register FRM_PR28 bit 4 is set to 1. Optionally, if LTS0MFA monitoring in the performance counters is enabled, by setting registers FRM_PR14 through FRM_PR17 bit 1 to 1, then these counts are incremented once per second for the duration of the LTS0MFA state.
s s
The CRC-4 bits in the SMF are replaced by binary 0s. The SMF is then acted upon the multiplication/division process referred to above. The remainder resulting from the multiplication/division process is stored, ready for insertion into the respective CRC-4 locations of the next SMF.
s
s s
s
The decoding procedure, as described in ITU Rec. G.704 Section 2.3.3.5.3, follows:
s
s
A received SMF is acted upon by the multiplication/ division process referred to above, after having its CRC-4 bits extracted and replaced by 0s. The remainder resulting from this division process is then stored and subsequently compared on a bit-bybit basis with the CRC bits received in the next SMF. If the remainder calculated in the decoder exactly corresponds to the CRC-4 bits received in the next SMF, it is assumed that the checked SMF is errorfree.
s
s
s
s
s
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms
Several optional algorithms exist in the receive framer. These are selected through programming of register FRM_PR9. CRC-4 Multiframe Alignment Algorithm with 8 ms Timer The default algorithm is as described in ITU Rec. G.706 Section 4.2. The recommendation states that if a condition of assumed frame alignment has been achieved, CRC-4 multiframe alignment is deemed to have occurred if at least two valid CRC-4 multiframe alignment signals can be located within 8 ms, the time separating two CRC-4 multiframe signals being 2 ms or a multiple of 2 ms. The search for the CRC-4 multiframe alignment signal is made only in bit 1 of NOT FAS frames. If multiframe alignment cannot be achieved within 8 ms, it is assumed that frame alignment is due to a spurious frame alignment signal and a new parallel search for basic frame alignment is initiated. The new search for the basic frame alignment is started at the point just after the location of the assumed spurious frame alignment signal. During this parallel search for basic frame alignment, there is no indication to the system of a receive loss of frame alignment (RLFA) state. During the parallel search for basic frame alignment and while in primary basic frame alignment, data will flow through the receive framer to the system interface as defined by the current primary frame alignment. The receive framer will continuously search for CRC-4 multiframe alignment.
CRC-4 Multiframe Alignment Algorithm with 100 ms Timer The CRC-4 multiframe alignment with 100 ms timer mode is enabled by setting FRM_PR9 to 0XXXX1X1 (binary). This CRC-4 multiframe reframe mode starts a 100 ms timer upon detection of basic frame alignment. This is a parallel timer to the 8 ms timer. If CRC-4 multiframe alignment cannot be achieved within the time limit of 100 ms due to the CRC-4 procedure not being implemented at the transmitting side, then an indication is given, and actions are taken equivalent to those specified for loss of basic frame alignment, namely:
s
Optional automatic transmission of A = 1 to the line if register FRM_PR27 bit 3 is set to 1. Optional automatic transmission of E = 0 to the line if register FRM_PR28 bit 5 is set to 1. Optional automatic transmission of AIS to the system if register FRM_PR19 bit 1 is set to 1.
s
s
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Frame Formats (continued)
OUT OF PRIMARY BFA: * OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM * OPTIONALLY TRANSMIT A = 1 AND E = 0 TO LINE * INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING
NO
PRIMARY BFA SEARCH?
YES IN PRIMARY BFA: * ENABLE TRAFFIC TO THE SYSTEM * TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE * START 8 ms AND 100 ms TIMERS * ENABLE PRIMARY BFA LOSS CHECKING PROCESS YES CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2 - NOTE 2) NO PARALLEL BFA SEARCH GOOD?
YES YES CAN CRC-4 MFA BE FOUND IN 8 ms? NO IS INTERNAL 100 ms TRX = 1 ? NO
NO 100 ms TIMER ELAPSED?
YES ASSUME CRC-4 MULTIFRAME ALIGNMENT: * CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA * ADJUST PRIMARY BFA IF NECESSARY SET 100 ms TIMER EXPIRATION STATUS BIT TO THE 1 STATE: SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 1: * OPTIONALLY TRANSMIT A BIT = 1 TO THE LINE INTERFACE FOR THE DURATION OF LTS0MFA = 1 * OPTIONALLY TRANSMIT AIS TO THE SYSTEM INTERFACE FOR THE DURATION OF LTS0MFA = 1 * OPTIONALLY TRANSMIT E BIT = 0 TO THE LINE INTERFACE FOR THE DURATION OF LTSOMFA = 1
YES IS 100 ms TRX = 1 ? NO
SET INTERNAL 100 ms TIMER EXPIRATION STATUS BIT TO 0: * IF TRANSMITTING A BIT = 1 TO THE LINE INTERFACE, TRANSMIT A BIT = 0 * IF TRANSMITTING AIS TO THE SYSTEM INTERFACE, ENABLE DATA TRANSMISSION TO THE SYSTEM INTERFACE * IF TRANSMITTING E = 0 TO THE LINE INTERFACE, TRANSMIT E BIT = 1
START CRC-4 PERFORMANCE MONITORING: * SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4
YES
CRC-4 COUNT > 914 IN 1 SECOND OR LFA = 1?
NO
CONTINUE CRC-4 PERFORMANCE MONITORING: * SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4
5-3909(F).er.2
Figure 13. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
CRC-4 Multiframe Alignment Search Algorithm with 400 ms Timer The CRC-4 multiframe alignment with 400 ms timer mode is enabled by setting FRM_PR9 to 0XXX1XX1 (binary). This receive CRC-4 multiframe reframe mode is the modified CRC-4 multiframe alignment algorithm described in ITU Rec. 706 Annex B, where it is referred to as CRC-4-to-non-CRC-4 equipment interworking. A flow diagram of this algorithm is illustrated in Figure 14. When the interworking algorithm is enabled, it supersedes the 100 ms algorithm described on page 51 and in Figure 13. This algorithm assumes that a valid basic frame alignment signal is consistently present, but the CRC-4 multiframe alignment cannot be achieved by the end of the total CRC-4 multiframe alignment search period of 400 ms, if the distant end is a non-CRC-4 equipment. In this mode, the following consequent actions are taken:
s
-- If 915 out of 1000 errored CRC-4 blocks are detected resulting in a loss of basic frame alignment as described in ITU Rec. G.706 Section 4.3.2. -- On-demand reframe is requested. -- The receive framer is programmed to the nonCRC-4 mode.
s
The loss of basic frame alignment checking process runs continuously, irrespective of the state of the CRC-4 multiframe alignment process below it. A new search for frame alignment is initiated if CRC-4 multiframe alignment cannot be achieved in 8 ms, as described in ITU Rec. G.706 Section 4.2. This new search for basic frame alignment will not reset the 400 ms timer or invoke consequent actions associated with loss of the primary basic frame alignment. In particular, all searches for basic frame alignment are carried out in parallel with, and independent of, the primary basic frame loss checking process. All subsequent searches for CRC-4 multiframe alignment are associated with each basic framing sequence found during the parallel search. During the search for CRC-4 multiframe alignment, traffic is allowed through, upon, and to be synchronized to, the initially determined primary basic frame alignment. Upon detection of the CRC-4 multiframe before the 400 ms timer elapsing, the basic frame alignment associated with the CRC-4 multiframe alignment replaces, if necessary, the initially determined basic frame alignment. If CRC-4 multiframe alignment is not found before the 400 ms timer elapses, it is assumed that a condition of interworking between equipment with and without CRC-4 capability exists and the actions described above are taken. If the 2.048 Mbits/s path is reconfigured at any time, then it is assumed that the (new) pair of path terminating equipment will need to re-establish the complete framing process, and the algorithm is reset.
s
An indication that there is no incoming CRC-4 multiframe alignment signal.
s
s
All CRC-4 processing on the receive 2.048 Mbits/s signal is inhibited. CRC-4 data is transmitted to the distant end with both E bits set to 0.
s
s
This algorithm allows the identification of failure of CRC-4 multiframe alignment generation/detection, but with correct basic framing, when interworking between each piece of equipment having the modified CRC-4 multiframe alignment algorithm. As described in ITU Rec. G.706 Section B.2.3:
s
s
A 400 ms timer is triggered on the initial recovery of the primary basic frame alignment. The 400 ms timer reset if and only if: -- The criteria for loss of basic frame alignment as described in ITU Rec. G.706 Section 4.1.1 is achieved.
s
s
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Frame Formats (continued)
OUT OF PRIMARY BFA: * OPTIONALLY DISABLE TRAFFIC BY TRANSMITTING AIS TO THE SYSTEM * OPTIONALLY TRANSMIT A BIT = 1 AND E BIT = 0 TO LINE * INHIBIT INCOMING CRC-4 PERFORMANCE MONITORING
NO
PRIMARY BFA SEARCH?
YES IN PRIMARY BFA: * ENABLE TRAFFIC NOT TRANSMITTING AIS TO THE SYSTEM * TRANSMIT A = 0 AND OPTIONALLY E = 0 TO THE LINE * START 400 ms TIMER * ENABLE PRIMARY BFA LOSS CHECKING PROCESS YES CRC-4 MFA SEARCH (ITU REC. G.706, SECTION 4.2) NO PARALLEL BFA SEARCH ?
NO YES CAN CRC-4 MFA BE FOUND IN 8 ms? NO 400 ms TIMER ELAPSED?
YES ASSUME CRC-4-TO-CRC-4 INTERWORKING: * CONFIRM PRIMARY BFA ASSOCIATED WITH CRC-4 MFA * ADJUST PRIMARY BFA IF NECESSARY * KEEP A = 0 IN OUTGOING CRC-4 DATA ASSUME CRC-4-TO-NON-CRC-4 INTERWORKING: * CONFIRM PRIMARY BFA * TRANSMIT A BIT = 0 TO THE LINE INTERFACE * TRANSMIT E BIT = 0 TO THE LINE INTERFACE * STOP INCOMING CRC-4 PROCESSING * INDICATE "NO CRC-4 MFA"
START CRC-4 PERFORMANCE MONITORING: * SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4
YES
CRC-4 COUNT > 914 IN 1 SECOND OR LFA = 1?
NO
CONTINUE CRC-4 PERFORMANCE MONITORING: * SET E BITS ACCORDING TO ITU REC. G.704, SECTION 2.3.3.4
5-3909(F).fr.3
Figure 14. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991)
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Frame Formats (continued)
CEPT Time Slot 16 Multiframe Structure
The TFRA08C13 supports two CEPT signaling modes: channel associated signaling (CAS) or per-channel signaling (PCS0 and PCS1). Channel Associated Signaling (CAS) The channel associated signaling (CAS) mode utilizes time slot 16 of the FAS and NOT FAS frames. The CAS format is a multiframe consisting of 16 frames where frame 0 of the multiframe contains the multiframe alignment pattern of four zeros in bits 1 through 4. Table 21 illustrates the CAS multiframe of time slot 16. The TFRA08C13 can be programmed to force the transmitted line CAS multiframe alignment pattern to be transmitted in the FAS frame by selecting the PCS0 option or in the NOT FAS frame by selecting the PCS1 option. Alignment of the transmitted line CAS multiframe to the CRC-4 multiframe is arbitrary. Table 21. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure Time Slot 16 Channel Associated Signaling Multiframe Frame Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit 1 0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 2 0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 3 0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 4 0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 5 X0 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 6 YM B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 7 X1 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 8 X2 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30
Notes: Frame 0 bits 1--4 define the time slot 16 multiframe alignment. X0--X2 = time slot 16 spare bits defined in FRM_PR41 bit 0--bit 2. YM = yellow alarm, time slot 16 remote multiframe alarm (RMA) bit (1 = alarm condition).
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55
TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Frame Formats (continued)
CEPT Loss of Time Slot 16 Multiframe Alignment (LTS16MFA)
Loss of basic frame alignment forces the receive framer into a loss of time slot 16 signaling multiframe alignment state. In addition, as defined in ITU Rec. G.732 Section 5.2, time slot 16 signaling multiframe is assumed lost when two consecutive time slot 16 multiframe 4-bit all-zero patterns is received with an error. In addition, the time slot 16 multiframe is assumed lost when, for a period of two multiframes, all bits in time slot 16 are in state 0. This state is reported by way of the status registers FRM_SR1 bit 1. Once basic frame alignment is achieved, the receive framer will initiate a search for the time slot 16 multiframe alignment. During a loss of time slot 16 multiframe alignment state, the following occurs:
s s s
CEPT Time Slot 0 FAS/NOT FAS Control Bits
FAS/NOT FAS Si- and E-Bit Source
The Si bit can be used as an 8 kbits/s data link to and from the remote end, or in the CRC-4 mode, it can be used to provide added protection against false frame alignment. The sources for the Si bits that are transmitted to the line are the following:
s
CEPT with no CRC-4 and FRM_PR28 bit 0 = 1: the TSiF control bit (FRM_PR28 bit 1) is transmitted in bit 1 of all FAS frames and the TSiNF control bit (FRM_PR28 bit 2) is transmitted in bit 1 of all NOT FAS frames. The CHI system interface (CEPT with no CRC-4 and FRM_PR28 bit 0 = 0)*. This option requires the received system data (RCHIDATA) to maintain a biframe alignment pattern where frames containing Si bit information for the NOT FAS frames have bit 2 of time slot 0 in the binary 1 state followed by frames containing Si bit information for the FAS frames that have bit 2 of time slot 0 in the binary 0 state. This ensures the proper alignment of the Si received system data to the transmit line Si data. Whenever this requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition (indication is given in the status registers) and then search for the pattern; in the loss of biframe alignment state, transmitted line data is corrupted (only when the system interface is sourcing Sa or Si data). When the transmit framer locates a new biframe alignment pattern, an indication is given in the status registers and the transmit framer resumes normal operations.
s
s
The updating of the signaling data is halted. The received control bits forced to the binary 1 state. The received remote multiframe alarm indication status bit is forced to the binary 0 state. Optionally, the transmit framer can transmit to the line the time slot 16 signaling remote multiframe alarm if register FRM_PR41 bit 4 is set to 1. Optionally, the transmit framer can transmit the alarm indication signal (AIS) in the system transmit time slot 16 data if register FRM_PR44 bit 6 is set to 1.
s
s
CEPT Loss of Time Slot 16 Multiframe Alignment Recovery Algorithm
The time slot 16 multiframe alignment recovery algorithm is as described in ITU Rec. G.732 Section 5.2. The recommendation states that if a condition of assumed frame alignment has been achieved, time slot 16 multiframe alignment is deemed to have occurred when the 4-bit time slot 16 multiframe pattern of 0000 is found in time slot 16 for the first time, and the preceding time slot 16 contained at least one bit in the binary 1 state.
* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001xxxxx (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)
s
s
CEPT with CRC-41: manual transmission of E bit = 0: -- If FRM_PR28 bit 0 = 0, then the TSiF bit (FRM_PR28 bit 1) is transmitted in bit 1 of frame 13 (E bit) and the TSiNF bit (FRM_PR28 bit 2) is transmitted in bit 1 of frame 15 (E bit). -- If FRM_PR28 bit 0 = 1, then each time 0 is written into TSiF (FRM_PR28 bit 1) one E bit = 0 is transmitted in frame 13, and each time 0 is written into TSiNF (FRM_PR28 bit 2) one E bit = 0 is transmitted in frame 15. CEPT with CRC-41, automatic transmission of E bit = 0: -- Optionally, one transmitted E bit is set to 0 by the transmit framer, as described in ITU Rec. G.704 Section 2.3.3.4, for each received errored CRC-4 submultiframe detected by the receive framer if FRM_PR28 bit 3 = 1. -- Optionally, as described in ITU Rec. G.704 Section 2.3.3.4, both E bits are set to 0 while in a received loss of CRC-4 multiframe alignment state2 if FRM_PR28 bit 4 = 1. -- Optionally, when the 100 ms or 400 ms timer is enabled and the timer has expired, as described in ITU Rec. G.706 Section B.2.2, both E bits are set to 0 for the duration of the loss of CRC-4 multiframe alignment state2 if FRM_PR28 bit 5 = 1.
s
Optionally for the following alarm conditions as selected through programming register FRM_PR27. -- The duration of loss of basic frame alignment as described in ITU Rec. G.706 Section 4.1.1 3, or ITU Rec. G.706 Section 4.3.24 if register FRM_PR27 bit 0 = 1. -- The duration of loss of CRC-4 multiframe alignment if register FRM_PR27 bit 2 = 1. -- The duration of loss of signaling time slot 16 multiframe alignment if register FRM_PR27 bit 1 = 1. -- The duration of loss of CRC-4 multiframe alignment after either the 100 ms or 400 ms timer expires if register FRM_PR27 bit 3 = 1. -- The duration of receive Sa6_8hex5 if register FRM_PR27 bit 4 = 1. -- The duration of receive Sa6_Chex5 if register FRM_PR27 bit 5 = 1.
NOT FAS Sa-Bit Sources6
The Sa bits, Sa4--Sa8, in the NOT FAS frame can be a 4 kbits/s data link to and from the remote end. The sources and value for the Sa bits are as follows:
s
The Sa source register FRM_PR29 bit 0--bit 4 if FRM_PR29 bit 7--bit 5 = 000 (binary) and FRM_PR30 bit 4--bit 0 = 11111 (binary). The facility data link external input (TFDL) if register FRM_PR29 bit 7 = 1 and register FRM_PR21 bit 6 = 1. The internal FDL-HDLC if register FRM_PR29 bit 7 = 1 and register FRM_PR21 bit 6 = 0. The Sa transmit stack if register FRM_PR29 bit 7--bit 5 are set to 01x (binary).
s
Otherwise, the E bits are transmitted to the line in the 1 state.
s
NOT FAS A-Bit (CEPT Remote Frame Alarm) Sources
The A bit, as described in ITU Rec. G.704 Section 2.3.2, Table 4a/G.704, is the remote alarm indication bit. In undisturbed conditions, this bit is set to 0 and transmitted to the line. In the loss of frame alignment (LFA) state, this bit may be set to 1 and transmitted to the line as determined by register FRM_PR27. The A bit is set to 1 and transmitted to the line for the following conditions:
s
s
Setting the transmit A bit = 1 control bit by setting register FRM_PR27 bit 7 to 1.
1. The receive E-bit processor will halt the monitoring of received E bits during loss of CRC-4 multiframe alignment. 2. Whenever loss of frame alignment occurs, then loss of CRC-4 multiframe alignment is forced. Once frame alignment is established, then and only then, is the search for CRC-4 multiframe alignment initiated. The receive framer unit, when programmed for CRC-4, can be in a state of LFA and LTS0MFA or in a state of LTS0MFA only, but cannot be in a state of LFA only. 3. LFA is due to framing bit errors. 4. LFA is due to detecting 915 out of 1000 received CRC-4 errored blocks. 5. See Table 29 . Sa6 Bit Coding Recognized by the Receive Framer, for a definition of this Sa6 pattern. 6. Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001xxxxx (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.
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Preliminary Data Sheet October 2000
The status of the received Sa bits and the received Sa stack is available in status register FRM_SR4. The transmit and receive Sa bit for the FDL can be selected by setting register FRM_PR43 bit 0--bit 2 as shown in Table 148.
CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)
s
The CHI system interface if register FRM_PR29 bit 7--bit 5 are set to 001 (binary). This option requires the received system data (RCHIDATA) to maintain a biframe alignment pattern where (1) frames containing Sa bit information have bit 2 of time slot 0 in the binary 1 state and (2) these NOT FAS frames are followed by frames not containing Sa bit information, the FAS frames, which have bit 2 of time slot 0 in the binary 0 state. This ensures the proper alignment of the Sa received system data to the transmit line Sa data. Whenever this requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition indicated in the status register, FRM_SR1 bit 4, and then search for the pattern. In the loss of biframe alignment state, transmitted line data is corrupted (only when the system interface is sourcing Sa or Si data). When the transmit framer locates a new biframe alignment pattern, an indication is given in the status registers and the transmit framer resumes normal operations.
Sa Facility Data Link Access
The data link interface may be used to source one of the Sa bits. Access is controlled by registers FRM_PR29, FRM_PR30, and FRM_PR43, see NOT FAS Sa-Bit Sources on page 57. The receive Sa data is always present at the receive facility data link output pin, RFDL, along with a valid clock signal at the receive facility clock output pin, RFDLCK. During a loss of frame alignment (LFA) state, the RFDL signal is forced to a 1 state while RFDLCK continues to toggle on the previous frame alignment. When basic frame alignment is found, RFDL is as received from the selected receive Sa bit position and RFDLCK is forced (if necessary) to the new alignment. The data rate for this access mode is 4 kHz. The access timing for the transmit and receive facility data is illustrated in Figure 15 below. During loss of receive clock (LOFRMRLCK), RFDL and RFDLCK are frozen in a state at the point of the LOFRMRLCK being asserted.
The receive Sa data is present at the following:
s
The Sa received stack, registers FRM_SR54-- FRM_SR63, if the TFRA08C13 is programmed in the Sa stack mode. The system transmit interface.
s
t8 TFDLCK t8: TFDLCK CYCLE = 250 s
t9
t9
TFDL
t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns
t10
t10: RFDLCK CYCLE = 250 s
RFDLCK
t11 RFDL
t11: RFDLCK TO RFDL DELAY = 40 ns
5-3910(F).dr.1
Figure 15. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT Mode 58 Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)
NOT FAS Sa Stack Source and Destination
The transmit Sa4 to Sa8 bits may be sourced from the transmit Sa stack, registers FRM_PR31--FRM_PR40. The Sa stack consists of ten 8-bit registers that contain 16 NOT FAS frames of Sa information as shown in Table 22. The transmit stack data may be transmitted either in non-CRC-4 mode or in CRC-4 mode to the line. The receive stack data, registers FRM_SR54--FRM_SR63, is valid in both the non-CRC-4 mode and the CRC-4 mode. In the non-CRC-4 mode while in the loss of frame alignment (LFA) state, updating of the receive Sa stack is halted and the transmit and receive stack interrupts are deactivated. In the CRC-4 mode while in the loss of time slot 0 multiframe alignment (LTS0MFA) state, updating of the receive Sa stack is halted and the transmit and receive stack interrupts are deactivated. Table 22. Transmit and Receive Sa Stack Structure Register Number 1 2 3 4 5 6 7 8 9 10 Bit 7 (MSB) Sa4-1 Sa4-17 Sa5-1 Sa5-17 Sa6-1 Sa6-17 Sa7-1 Sa7-17 Sa8-1 Sa8-17 Bit 6 Sa4-3 Sa4-19 Sa5-3 Sa5-19 Sa6-3 Sa6-19 Sa7-3 Sa7-19 Sa8-3 Sa8-19 Bit 5 Sa4-5 Sa4-21 Sa5-5 Sa5-21 Sa6-5 Sa6-21 Sa7-5 Sa7-21 Sa8-5 Sa8-21 Bit 4 Sa4-7 Sa4-23 Sa5-7 Sa5-23 Sa6-7 Sa6-23 Sa7-7 Sa7-23 Sa8-7 Sa8-23 Bit 3 Sa4-9 Sa4-25 Sa5-9 Sa5-25 Sa6-9 Sa6-25 Sa7-9 Sa7-25 Sa8-9 Sa8-25 Bit 2 Sa4-11 Sa4-27 Sa5-11 Sa5-27 Sa6-11 Sa6-27 Sa7-11 Sa7-27 Sa8-11 Sa8-27 Bit 1 + Sa4-13 Sa4-29 Sa5-13 Sa5-29 Sa6-13 Sa6-29 Sa7-13 Sa7-29 Sa8-13 Sa8-29 Bit 0 (LSB) Sa4-15 Sa4-31 Sa5-15 Sa5-31 Sa6-15 Sa6-31 Sa7-15 Sa7-31 Sa8-15 Sa8-31
The most significant bit of the first byte is transmitted to the line in frame 1 of a double CRC-4 multiframe. The least significant bit of the second byte is transmitted to the line in frame 31 of the double CRC-4 multiframe. The protocol for accessing the Sa Stack information for the transmit and receive Sa4 to Sa8 bits is shown in Figure 16 and described briefly below. The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 7 (CEPT transmit Sa stack ready) high. At this time, the system has about 4 ms to update the stack. Data written to the stack during this interval will be transmitted during the next double CRC-4 multiframe. By reading register FRM_SR4 bit 7, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the transmit stack is not updated, then the content of the stack is retransmitted to the line. The 32-frame interval of the transmit framer in the non-CRC-4 mode is arbitrary. Enabling transmit CRC-4 mode forces the updating of the internal transmit stack at the end of the 32-frame CRC-4 double multiframe; the transmit Sa stack is then transmitted synchronous to the transmit CRC-4 multiframe structure. On the receive side, the TFRA08C13 indicates that it has received data in the receive Sa stack, register FRM_SR54--FRM_SR63, by setting register FRM_SR4 bit 6 (CEPT receive Sa stack ready) high. The system then has about 4 ms to read the contents of the stack before it is updated again (old data lost). By reading register FRM_SR4 bit 6, the system clears this bit so that it can indicate the next time the receive stack is ready. The receive framer always updates the content of the receive stack so unread data will be overwritten. The last 16 valid Sa4 to Sa8 bits are always stored in the receive Sa stack on a double-multiframe boundary. The 32-frame interval of the receive framer in the non-CRC-4 mode is arbitrary. Enabling the receive CRC-4 mode forces updating of the receive Sa stack at the end of the 32-frame CRC-4 double multiframe. The receive Sa stack is received synchronous to the CRC-4 multiframe structure.
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CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)
SYSTEM ACCESS Sa STACK (SASS) INTERVAL: 1) TRANSMIT FRAMER UNIT TRANSMITS TO THE LINE THE DATA IN THE TRANSMIT Sa STACK WRITTEN DURING THE PREVIOUS SASS INTERVAL. 2) THE SYSTEM CAN UPDATE THE TRANSMIT Sa STACK REGISTERS FOR TRANSMISSION IN THE NEXT CRC-4 DOUBLE MULTIFRAME. 3) THE SYSTEM CAN READ THE RECEIVE Sa STACK REGISTERS TO ACCESS THE Sa BITS EXTRACTED DURING THE PREVIOUS VALID (IN MULTIFRAME ALIGNMENT) DOUBLE CRC-4 MULTIFRAME.
START OF CRC-4 DOUBLE MULTIFRAME: * BASIC FRAME ALIGNMENT FOUND, OR, * CRC-4 MULTIFRAME ALIGNMENT FOUND. SYSTEM ACCESS Sa STACK INTERVAL 1-FRAME INTERVAL 1 FRAME 31 FRAMES CRC-4 DOUBLE MULTIFRAME (DMF): 32 FRAMES START FRAME 1 OF 32 IN DMF. 31 FRAMES CRC-4 DOUBLE MULTIFRAME: 32 FRAMES
INTERNAL Sa STACK UPDATE INTERVAL
SYSTEM ACCESS IS DISABLED DURING THIS INTERVAL: 1) THE INTERNAL TRANSMIT Sa STACK IS UPDATED FROM THE FRAMER UNIT'S 10-byte TRANSMIT STACK CONTROL REGISTERS DURING THIS 1-FRAME INTERVAL. 2) ACCESS TO THE STACK CONTROL REGISTERS IS DISABLED DURING THIS 1-FRAME INTERVAL. 3) ONCE LOADED, THE INFORMATION IN THE INTERNAL TRANSMIT Sa STACK IS TRANSMITTED TO THE LINE DURING THE NEXT CRC-4 DOUBLE MULTIFRAME, ALIGNED TO THE CRC-4 MULTIFRAME. 4) IF THE TRANSMIT Sa STACK IS NOT UPDATED, THEN THE CONTENT OF THE TRANSMIT Sa STACKS IS RETRANSMITTED TO THE LINE. 5) THE SYSTEM READ-ONLY RECEIVE STACK IS UPDATED FROM THE INTERNAL RECEIVE STACK INFORMATION REGISTERS. 6) IN NON-CRC-4 MODE, THE RECEIVE Sa STACK EXTRACTING CIRCUITRY ASSUMES AN ARBITRARY DOUBLE 16-FRAME MULTIFRAME STRUCTURE (32 FRAMES), AND DATA IS EXTRACTED ONLY IN THE FRAME ALIGNED STATE. 7) IN CRC-4 MODE, THE RECEIVE Sa STACK INFORMATION IS ALIGNED TO A CRC-4 DOUBLE MULTIFRAME STRUCTURE (32 FRAMES), AND THE DATA IS EXTRACTED ONLY IN CRC-4 MULTIFRAME ALIGNED STATE.
5-3911(F).c
Figure 16. Transmit and Receive Sa Stack Accessing Protocol
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TFRA08C13 OCTAL T1/E1 Framer
CEPT Time Slot 0 FAS/NOT FAS Control Bits (continued)
Interrupts indicating that the transmit Sa stack or the receive Sa stack are ready for system access are available, see register FRM_SR4 bit 6 and bit 7.
CEPT Time Slot 16 X0--X2 Control Bits
Each of the three X bits in frame 0 of the time slot 16 multiframe can be used as a 0.5 kbits/s data link to and from the remote end. The transmitted line X bits are sourced from control register FRM_PR41 bit 0--bit 2. In the loss of TS16 multiframe alignment (LTS16MFA) state, receive X bits are set to 1 in status register FRM_SR53.
The receive-channel robbed-bit signaling mode is always defined by the state of the F and G bits in the corresponding transmit signaling registers for that channel. The received signaling data is stored in the receive signaling registers, FRM_RSR0-- FRM_RSR23, while receive framer is in both the frame and superframe alignment states. Updating the receive signaling registers can be inhibited on-demand, by setting register FRM_PR44 bit 3 to 1, or automatically when either a framing error event, a loss of frame, or superframe alignment state is detected or a controlled slip event occurs. The signaling inhibit state is valid for at least 32 frames after any one of the following: a framing errored event, a loss of frame and/or superframe alignment state, or a controlled slip event. In the common channel signaling mode, data written in the transmit signaling registers is transmitted in channel 24 of the transmit line bit stream. The F and G bits are ignored in this mode. The received signaling data from channel 24 is stored in receive signaling registers FRM_RSR0--FRM_RSR23 for T1. Associated Signaling Mode This mode is enabled by setting register FRM_PR44 bit 2 to 1. Signaling information in the associated signaling mode (ASM) is allocated an 8-bit system time slot in conjunction with the payload data information for a particular channel. The default system data rate in the ASM mode is 4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its corresponding 8-bit signaling time slot. The format of the signaling byte is identical to that of the signaling registers. In the ASM mode, writing the transmit signaling registers will corrupt the transmit signaling data. In the transmit signaling register ASM (TSR-ASM) format, enabled by setting register FRM_PR44 bit 2 and bit 5 to 1, the system must write into the F and G bit* of the transmit signaling registers to program the robbed-bit signaling state mode of each DS0. The ABCD bits are sourced from the RCHI ports when TSR-ASM mode is enabled.
Signaling Access
Signaling information can be accessed by three different methods: transparently through the CHI, via the control registers, or via the CHI associated signaling mode.
Transparent Signaling
This mode is enabled by setting register FRM_PR44 bit 0 to 1. Data at the received RCHIDATA interface passes through the framer undisturbed. The framer generates an arbitrary signaling multiframe in the transmit and receive directions to facilitate the access of signaling information at the system interface.
DS1: Robbed-Bit Signaling
Microprocessor Control Registers To enable signaling, register FRM_PR44 bit 0 must be set to 0 (default). The information written into the F and G bits of the transmit signaling registers, FRM_TSR0-- FRM_TSR23, define the robbed-bit signaling mode for each channel for both the transmit and receive directions. The per-channel programming allows the system to combine voice channels with data channels within the same frame.
* All other bits in the signaling registers are ignored, while the F and G bits in the received RCHIDATA stream are ignored.
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Signaling Access (continued)
Table 23 illustrates the ASM time-slot format for valid channels. Table 23. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames DS1: ASM CHI Time Slot 1 2 3 PAYLOAD DATA 4 5 6 7 8 A B SIGNALING INFORMATION* C D X F G P
* X indicates bits that are undefined by the framer. The identical sense of the received system P bit in the transmitted signaling data is echoed back to the system in the received signaling information.
The DS1 framing formats require rate adaptation from the line-interface 1.544 Mbits/s bit stream to the systeminterface 4.096 Mbits/s bit stream. The rate adaptation results in the need for stuffed time slots on the system interface. Table 24 illustrates the ASM format for T1 stuffed channels used by the TFRA08C13. The stuffed data byte contains the programmable idle code in register FRM_PR23 (default = 7F (hex)), while the signaling byte is ignored. Table 24. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels ASM CHI Time Slot 0 1 1 PAYLOAD DATA 1 1 1 1 1 X X SIGNALING INFORMATION* X X X X X X
* X indicates bits which are undefined by the framer.
CEPT: Time Slot 16 Signaling
Microprocessor Control Registers To enable signaling, register FRM_PR44 bit 0 must be set to 0 (default). The information written into transmit signaling control registers FRM_TSR0--FRM_TSR31 define the state of the ABCD bits of time slot 16 transmitted to the line. The received signaling data from time slot 16 is stored in receive signaling registers FRM_RSR0--FRM_RSR31. Associated Signaling Mode Signaling information in the associated signaling mode (ASM), register FRM_PR44 bit 2 = 1, is allocated an 8-bit system time slot in conjunction with the data information for a particular channel. The default system data rate in the ASM mode is 4.096 Mbits/s. Each system channel consists of an 8-bit payload time slot followed by its associated 8-bit signaling time slot. The format of the signaling byte is identical to the signaling registers. Table 25 illustrates the ASM time-slot format for valid CEPT E1 time slots Table 25. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT CEPT ASM CHI Time Slot PAYLOAD DATA 1 2 3 4 5 6 7 8 A B SIGNALING INFORMATION C D E X* X* P
* In the CEPT formats, these bits are undefined. The P bit is the parity-sense bit calculated over the 8 data bits, the ABCD (and E) bits, and the P bit. The identical sense of the received system P bit in the transmitted signaling data is echoed back to the system in the received signaling information.
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TFRA08C13 OCTAL T1/E1 Framer
Auxiliary Framer I/O Timing
Transmit and receive timing and data signals are provided by terminals RFRMCK (receive framer clock), RFRMDATA (receive framer data), RFS (receive frame sync), RSSFS (receive framer signaling superframe sync), RCRCMFS (receive frame CRC-4 multiframe sync), TFS (transmit framer frame sync), TSSFS (transmit framer signaling superframe sync), TCRCMFS (transmit framer CRC-4 multiframe sync). The receive signals are synchronized to the recovered receive line clock, RLCK, and the transmit signals are synchronized to the transmit line clock, TLCK. Note that TLCK must be phase locked to the CHI clock, CHICK, see Table 2. Pin Descriptions, pin D18. Detailed timing specifications for these signals are given in Figure 17--Figure 24.
RFRMCK 125 s RFS
RFRMDATA
BIT 7
BIT 0
BIT 1 TIME SLOT 1
TIME SLOT 24 DATA VALID
5-6290(F)r.6
Figure 17. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode
TLCK 125 s TFS
TPD (SINGLE RAIL) F BIT BIT 0 (MSB)
TS1
TS2
TS24 F BIT BIT 0 (MSB)
TS1
5-6292(F)r.7
Figure 18. Timing Specification for TFS, TLCK, and TPD in DS1 Mode
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Auxiliary Framer I/O Timing (continued)
RFRMCK 125 s RFS
RFRMDATA
BIT 7
BIT 0
BIT 1 FAS/NFAS: TIME SLOT 0
TIME SLOT 31
DATA VALID
5-6294(F)r.6
Figure 19. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode
RFRMCK 125 s RFS 2 ms RSSFS
RFRMDATA TS0 OF THE FRAME AFTER THE FRAME CONTAINING THE SIGNALING MULTIFRAME PATTERN (0000) TS0 OF THE FRAME AFTER THE FRAME CONTAINING THE SIGNALING MULTIFRAME PATTERN (0000)
5-6295(F)r.8
Figure 20. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode
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TFRA08C13 OCTAL T1/E1 Framer
Auxiliary Framer I/O Timing (continued)
RFRMCLK
RFS 2 ms RCRCMFS
RFRMDATA TS0 OF FRAME #0 OF MULTIFRAME TS0 OF FRAME #0 OF MULTIFRAME
5-6296(F)r.5
Figure 21. Timing Specification for RCRCMFS in CEPT Mode
TLCK 125 s TFS
TPD (SINGLE RAIL)
TS0 OF FRAME X
TS0 OF FRAME X + 1
5-6297(F)r.5
Figure 22. Timing Specification for TFS, TLCK, and TPD in CEPT Mode
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Auxiliary Framer I/O Timing (continued)
TFS 11 CLOCK CYCLES TLCK 2 ms TSSFS
TPD (SINGLE RAIL) TS0 OF THE FRAME CONTAINING THE SIGNALING MULTIFRAME PATTERN (0000)
5-6298(F)r.5
Figure 23. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode
TLCK
TFS 1 ms TCRCMFS 1 ms
TPD (SINGLE RAIL) TS0 OF FRAME #0 OF MULTIFRAME TS0 OF FRAME #8 OF MULTIFRAME TS0 OF FRAME #0 OF MULTIFRAME
5-6299(F)r.5
Figure 24. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode
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TFRA08C13 OCTAL T1/E1 Framer
Alarms and Performance Monitoring
Interrupt Generation
A global interrupt (pin AD8) may be generated if enabled by register GREG1. This interrupt is clocked using channel 1 framer receive line clock (RLCK1). If RLCK1 is absent, the interrupt is clocked using RLCK2, the receive line clock of channel 2. If both RLCK1 and RLCK2 are absent, clocking of interrupts is controlled by an interval 2.048 MHz clock generated from the CHI clock. Timing of the interrupt is shown in Figure 25. There is no relation between MPCK (pin AE10) and the interrupt, i.e., MPCK maybe asynchronous with any of the other TFRA08C13 clocks.
RLCK1
INTERRUPT (PIN AD8)
5-6563(F).ar.1
Figure 25. Relation Between RLCK1 and Interrupt (Pin AD8)
Alarm Definition
The receive framer monitors the receive line data for alarm conditions and errored events, and then presents this information to the system through the microprocessor interface status registers. The transmit framer, to a lesser degree, monitors the receive system data and presents the information to the system through the microprocessor interface status registers. Updating of the status registers is controlled by the receive line clock signal. When the receive loss of clock monitor determines that the receive line clock signal is lost, the system clock is used to clock the status registers and all status information should be considered corrupted. Although the precise method of detecting or generating alarm and error signals differs between framing modes, the functions are essentially the same. The alarm conditions monitored on the received line interface are:
s
Red alarm or the loss of frame alignment indication (FRM_SR1 bit 0). The red alarm indicates that the receive frame alignment for the line has been lost and the data cannot be properly extracted. The red alarm is indicated by the loss of frame condition for the various framing formats as defined in Table 26.
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Alarms and Performance Monitoring (continued)
Table 26. Red Alarm or Loss of Frame Alignment Conditions Framing Format D4 Number of Errored Framing Bits That Will Cause a Red Alarm (Loss of Frame Alignment) Condition 2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if PRM_PR10 bit 2 = 0. 2 errored frame bits (FT or FS) out of 4 consecutive frame bits if FRM_PR10 bit 2 = 1. 2 errored FT bits out of 4 consecutive FT bits if FRM_PR10 bit 2 = 0. 3 errored frame bits (FT or FS) or channel 24 FAS pattern out of 12 consecutive frame bits. 2 errored FE bits out of 4 consecutive FE bits or, optionally, 320 or more CRC6 errored checksums within a one second interval if loss of frame alignment due to excessive CRC-6 errors is enabled in FRM_PR9. Three consecutive incorrect FAS patterns or three consecutive incorrect NOT FAS patterns; or optionally, greater than 914 received CRC-4 checksum errors in a one second interval if loss of frame alignment due to excessive CRC-6 errors is enabled in FRM_PR9.
SLC-96
DDS: Frame ESF
CEPT
s
Yellow alarm or the remote frame alarm (FRM_SR1 bit 0). This alarm is an indication that the line remote end is in a loss of frame alignment state. Indication of remote frame alarm (commonly referred to as a yellow alarm) as for the different framing formats is shown in Table 27.
Table 27. Remote Frame Alarm Conditions Framing Format Superframe: D4 Superframe: D4-Japanese Superframe: DDS Extended Superframe (ESF) CEPT: Basic Frame CEPT: Signaling Multiframe
s
Remote Frame Alarm Format Bit 2 of all time slots in the 0 state. The twelfth (12th) framing bit in the 1 state in two out of three consecutive superframes. Bit 6 of time slot 24 in the 0 state. An alternating pattern of eight ones followed by eight 0s in the ESF data link. Bit 3 of the NOT FAS frame in the 1 state in three consecutive frames. Bit 6 of the time slot 16 signaling frame in the 1 state.
Blue alarm or the alarm indication signal (AIS). The alarm indication signal (AIS), sometimes referred to as the blue alarm, is an indication that the remote end is out-of-service. Detection of an incoming alarm indication signal is defined in Table 29.
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TFRA08C13 OCTAL T1/E1 Framer
Alarms and Performance Monitoring (continued)
Table 28. Alarm Indication Signal Conditions Framing Format T1 CEPT ETSI Remote Frame Alarm Format Loss of frame alignment occurs and the incoming signal has two or fewer zeros in each of two consecutive double frame periods (386 bits). As described in ETSI ETS 300 233: May 1994, Section 8.2.2.4, loss of frame alignment occurs and the framer receives a 512 bit period containing two or less binary zeros. This is enabled by setting register FRM_PR10 bit 1 to 0. As described in ITU Rec. G.775, the incoming signal has two or fewer zeros in each of two consecutive double frame periods (512 bits). AIS is cleared if each of two consecutive double frame periods contains three or more zeros or frame alignment signal (FAS) has been found. This is enabled by setting register FRM_PR10 bit 1 to 1.
CEPT ITU
s
The SLIP condition (FRM_SR3 bit 6 and bit 7). SLIP is defined as the state in which the receive elastic store buffer's write address pointer from the receive framer and the read address pointer from the transmit concentration highway interface are equal *. -- The negative slip (Slip-N) alarm indicates that the receive line clock (RLCK) - transmit CHI clock (CHICK) monitoring circuit detects a state of overflow caused by RLCK and CHICK being out of phase-lock and the period of the received frame being less than that of the system frame. One system frame is deleted. -- The positive slip (Slip-P) alarm indicates the line clock (RLCK) - transmit CHI clock (CHICK) monitoring circuit detects a state of underflow caused by RLCK and CHICK being out of phase-lock and the period of the received frame being greater than that of the system frame. One system frame is repeated. The loss of framer receive clock (LORLCK, pin G23). The LORLCK alarm is asserted high when an interval of 250 ms has expired with no transition of RLCK (pin see Table 2. Pin Descriptions) detected. The alarm is disabled on the first transition of RLCK. Bit 0--bit 2 of global register 8 (GREG8) determine which framer sources the LORLCK pin (see Table 69 Interrupt Status Register (FRM_SR0) (Y00)). The loss of PLL clock (LOPLLCK, pin F25). LOPLLCK alarm is asserted high when an interval of 250 ms has expired with no transition of PLLCK (pin see Table 2 . Pin Descriptions) detected. The alarm is disabled 250 s after the first transition of PLLCK. Timing for LOPLLCK is shown in Figure 26. Bit 0--bit 2 of global register 8 (GREG8) determine which framer sources the LOPLLCK pin (see Table 69).
s
s
PLLCK 250 s LOPLLCK 250 s
CHICK
5-6564(F).a
Figure 26. Timing for Generation of LOPLLCK (Pin F25)
* After a reset, the read and write pointers of the receive path elastic store will be set to a known state.
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s
Alarms and Performance Monitoring
(continued)
s
Received bipolar violation errors alarm, FRM_SR3 bit 0. This alarm indicates any bipolar decoding error or detection of excessive zeros. Received excessive CRC errors alarm, FRM_SR3 bit 3. In ESF, this alarm is asserted when 320 or more CRC-6 checksum errors are detected within a one second interval. In CEPT, this alarm is asserted when 915 or more CRC-4 checksum errors are detected within a one second interval. The CEPT continuous E-bit alarm (CREBIT) (FRM_SR2 bit 2). CREBIT is asserted when the receive framer detects the following: -- Five consecutive seconds where each 1 s interval contains 991 received E bits = 0 events. -- Simultaneously no LFA occurred. -- Optionally, no remote frame alarm (A bit = 1) was detected if register FRM_PR9 bit 0, bit 4, and bit 5 are set to 1. -- Optionally, neither Sa6-Fhex nor Sa6-Ehex codes were detected if register FRM_PR9 bit 0, bit 4, and bit 6 are set to 1. The 5 s timer is started when the following occurs: -- CRC-4 multiframe alignment is achieved. -- And optionally, A = 0 is detected if register FRM_PR9 bit 0, bit 4, and bit 5 are set to 1. -- And optionally, neither Sa6_Fhex* nor Sa6_Ehex* is detected if register FRM_PR9 bit 0, bit 4, and bit 6 are set to 1. The 5 s counter is restarted when the following occurs: -- LFA occurs, or -- 990 E bit = 0 events occur in 1 s, or -- Optionally, an A bit = 1 is detected if register FRM_PR9 bit 0, bit 4, and bit 5 are set to 1. -- Optionally, a valid Sa6 pattern 1111 (binary) or Sa6 pattern 1110 (binary) code was detected if register FRM_PR9 bit 0, bit 4, and bit 6 are set to 1.
s
Failed state alarm or the unavailable state alarm, FRM_SR5 bit 3 and bit 7 and FRM_SR6 bit 3 and bit 7. This alarm is defined as the unavailable state at the onset of ten consecutive severely errored seconds. In this state, the receive framer inhibits incrementing of the severely errored and errored second counters for the duration of the unavailable state. The receive framer deasserts the unavailable state condition at the onset of ten consecutive errored seconds which were not severely errored. The 4-bit Sa6 codes (FRM_SR2 bit 3--bit 7). Sa6 codes are asserted if three consecutive 4-bit patterns have been detected. The alarms are disabled when three consecutive 4-bit Sa6 codes have been detected that are different from the pattern previously detected. The receive framer monitors the Sa6 bits for special codes described in ETSI ETS 300 233: May 1994, Section 9.2. The Sa6 codes are defined in Table 29 and Table 30. The Sa6 codes in Table 29 may be recognized as an asynchronous bit stream in either non-CRC-4 or CRC-4 modes as long as the receive framer is in the basic frame alignment state. In the CRC-4 mode, the receive framer can optionally recognize the received Sa6 codes in Table 29 synchronously to the CRC-4 submultiframe structure as long as the receive framer is in the CRC-4 multiframe alignment state (synchronous Sa6 monitoring can be enabled by setting register FRM_PR10 bit 1 to 1). The Sa6 codes in Table 30 are only recognized synchronously to the CRC-4 submultiframe and when the receive framer is in CRC-4 multiframe alignment. The detection of three (3) consecutive 4-bit patterns are required to indicate a valid received Sa6 code. The detection of Sa6 codes is indicated in status register FRM_SR2 bit 3--bit 7. Once set, any three-nibble (12-bit) interval that contains any other Sa6 code will clear the current Sa6 status bit. Interrupts may be generated by the Sa6 codes given in Table 29
s
s
* See Table 29, for the definition of this Sa6 pattern.
This alarm is disabled during loss of frame alignment (LFA) or loss of CRC-4 multiframe alignment (LTS0MFA).
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TFRA08C13 OCTAL T1/E1 Framer
Alarms and Performance Monitoring (continued)
Table 29. Sa6 Bit Coding Recognized by the Receive Framer Code Sa6_8hex Sa6_Ahex Sa6_Chex Sa6_Ehex Sa6_Fhex First Receive Bit (MSB) 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 Last Received Bit (LSB) 0 0 0 0 1
Table 30 defines the three 4-bit Sa6 codes that are always detected synchronously to the CRC-4 submultiframe structure, and are only used for counting NT1 events. Table 30. Sa6 Bit Coding of NT1 Interface Events Recognized by the Receive Framer Code Sa6_1hex Sa6_2hex Sa6_3hex First Receive Bit (MSB) 0 0 0 0 0 0 0 1 1 Last Received Bit (LSB) 1 0 1 Event at NT1 E=0 CRC-4 Error CRC-4 Error & E = 0 This code will cause both counters to increment. Counter Size (bits) 16 16 --
The reference points for receive CRC-4, E-bit, and Sa6 decoding are illustrated in Figure 27
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Alarms and Performance Monitoring (continued)
T REFERENCE POINT NT2 (NT1 REMOTE) NT1
V REFERENCE POINT ET
CRC ERROR DETECTED
CRC ERROR DETECTED
E BIT = 0
CRC-4 ERRORS AT THE ET, E BIT = 0, ERROR EVENT AT THE ET REMOTE
E BIT = 0
Sa6 CRC-4 ERRORS DETECTED FROM NT1 REMOTE, THEN SET Sa6 = 001X E = 0 DETECTED FROM NT1 REMOTE, THEN SET Sa6 = 00X1 CRC-4 ERRORS AT THE NT1 E BIT = 0, ERROR EVENT DETECTED AT THE NT1 REMOTE COUNT: 1) CRC ERRORS, 2) E = 0, 3) Sa6 = 001X, AND 4) Sa6 = 00X1
5-3913(F)r.8
Figure 27. The T and V Reference Points for a Typical CEPT E1 Application CEPT auxiliary pattern alarm (AUXP) (FRM_SR1 bit 6). The received auxiliary alarm, register FRM_SR1 bit 6 (AUXP), is asserted when the receive framer is in the LFA state and has detected more than 253 10 (binary) patterns for 512 consecutive bits. In a 512-bit interval, only two 10 (binary) patterns are allowable for the alarm to be asserted and maintained. The 512-bit interval is a sliding window determined by the first 10 (binary) pattern detected. This alarm is disabled when three or more 10 (binary) patterns are detected in 512 consecutive bits. The search for AUXP is synchronized with the first alternating 10 (binary) pattern as shown in Table 31.
s
Table 31. AUXP Synchronization and Clear Sychronization Process 00 -- 10 sync 10 -- 01 -- 11 -- 11 clear sync 00 -- 00 -- 0 -- 10 sync 00 ... 10 ...
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Alarms and Performance Monitoring (continued)
Event Counters Definition
The error events monitored in the receive framer's status registers are defined in Table 32 for the hardwired (default) threshold values. The errored second and severely errored second threshold registers can be programmed through FRM_PR11--FRM_PR13 such that the errored and severely errored second counters function as required by system needs. DS1 errors are reported in the ET Error registers, FRM_SR20 through FRM_SR35. For the framer to correctly report coding and BPV errors, the LIU/Framer interface must be configured as dual rail mode. Table 32. Event Counters Definition Error Event Bipolar Violations (BPVs) Functional Mode AMI B8ZS CEPT HDB3 SF: D4 Frame Alignment Errors (FERs) SF: SLC-96 SF: DDS ESF CEPT Definition Any bipolar violation or 16 or more consecutive zeros Any BPV, code violation, or any 8-bit interval with no one pulse Any BPV, code violation, or any 4-bit interval with no one pulse Any FT or FS bit errors (FRM_PR10 bit 2 = 1) or any FT bit errors (FRM_PR10 bit 2 = 0) Any FT or FS bit errors (FRM_PR10 bit 2 = 1) or any FT bit errors (FRM_PR10 bit 2 = 0) Any FT, FS, or time slot 24 FAS bit error Any FE bit error Any FAS (0011011) or NOT FAS (bit 2) bit error if register FRM_PR10, bit 2 = 0. Any FAS (0011011) bit error if register FRM_PR10, bit 2 = 1. Any received checksum in error Counter Size (bits) 16
16
CRC Checksum ESF or CEPT with CRC Errors Excessive CRC ESF Errors CEPT with CRC Received CEPT with CRC-4 E bits = 0 Errored Second All Events
16 NONE 16 16
320 checksum errors in a one second interval 915 checksum errors in a one second interval
E bits = 0 in frame 13 and frame 15
Any one of the relevant error conditions enabled in registers FRM_PR14--FRM_PR18 within a one second interval DS1: non-ESF Any framing bit errors within a one second interval DS1: ESF Any CRC-6 errors within a one second interval CEPT without CRC-4 Any framing errors within a one second interval CEPT with CRC-4 (ET1) Any CRC-4 errors within a one second interval CEPT with CRC-4 Any E bit = 0 event within a one second interval (ET1 remote) CEPT with CRC-4 (NT1) Any Sa6 = 001x (binary) code event within a one second interval CEPT with CRC-4 Any Sa6 = 00x1 (binary) code event within a one (NT1 remote) second interval
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Alarms and Performance Monitoring (continued)
Table 32. Event Counters Definition (continued) Error Event Bursty Errored Second Events Functional Mode DS1: non-ESF DS1: ESF CEPT without CRC-4 CEPT with CRC-4 (ET1) CEPT with CRC-4 (ET1 remote) CEPT with CRC-4 (NT1) CEPT with CRC-4 (NT1 remote) Severely Errored All Second Events DS1: non-ESF DS1: ESF CEPT with no CRC-4 CEPT with CRC-4 (ET1) CEPT with CRC-4 (ET1 remote) CEPT with CRC-4 (NT1) CEPT with CRC-4 (NT1 remote) All Definition Greater than 1 but less than 8 framing bit errors within a one second interval Greater than 1 but less than 320 CRC-6 errors within a one second interval Greater than 1 but less than 16 framing bit errors within a one second interval Greater than 1 but less than 915 CRC-4 errors within a one second interval Greater than 1 but less than 915 E bit = 0 events within a one second interval Greater than 1 but less than 915 Sa6=001x (binary) code events within a one second interval Greater than 1 but less than 915 Sa6=00x1 (binary) code events within a one second interval Any one of the relevant error conditions enabled in registers FRM_PR14--FRM_PR18 within a one second interval 8 or more framing bit errors within a one second interval 320 or more CRC-6 errors within a one second interval 16 or more framing bit errors within a one second interval 915 or more CRC-4 errors within a one second interval 915 or more E bit = 0 events within a one second interval 915 or more Sa6=001x (binary) code events within a one second interval 915 or more Sa6=00x1 (binary) code events within a one second interval A one second period in the unavailable state Counter Size (bits) 16
16
Unavailable Second Events
16
The receive framer enters an unavailable state condition at the onset of ten consecutive severely errored second events. When in the unavailable state, the receive framer deasserts the unavailable state alarms at the onset of ten consecutive seconds which were not severely errored.
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TFRA08C13 OCTAL T1/E1 Framer
Alarms and Performance Monitoring
(continued)
s
Loopback and Transmission Modes
Primary Loopback Modes Framer primary loopback mode is controlled by register FRM_PR24. There are seven primary loopback and transmission test modes supported:
s s s s s s s
Line loopback (LLB). Board loopback (BLB). Single time-slot system loopback (STSSLB). Single time-slot line loopback (STSLLB). CEPT nailed-up broadcast transmission (CNUBT). Payload loopback (PLLB). CEPT nailed-up connect loopback (CNUCLB).
s s
The STSLLB mode loops one and only one received line time slot back to the transmit line. The selected time-slot data is looped to the line after being processed by the receive framer, and it passes through the receive elastic store. The selected time slot has the programmable idle code in register FRM_PR22 transmitted to the system interface one frame before implementing the loopback and for the duration of the loopback. In CEPT, selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will not be looped back to the line and should not be chosen). This mode can be selected by setting register FRM_PR24 to 100A4A3A2A1A0, where A4A3A2A1A0 is the binary address of the selected time slot. The CNUBT mode transmits received-line time slot X to the system in time slot X and time slot 0 (of the next frame). Any time slot can be broadcast. This mode can be selected by setting register FRM_PR24 to 101A4A3A2A1A0 where A4A3A2A1A0 is the binary address of the selected time slot. The PLLB mode loops the received line data and clock back to the transmit line while inserting (replacing) the facility data link in the looped back data. Two variations of the payload loopback are available. In the pass-through framing/CRC bit mode (chosen by setting register FRM_PR24 to 111xxxxx (binary)), the framing and CRC bits are looped back to the line transmit data. In the regenerated framing/CRC bit mode (chosen by setting register FRM_PR24 to 110xxxxx (binary) and register FRM_PR10 bit 3 to 0), the framing and CRC bits are regenerated by the transmit framer. The payload loopback is only available for ESF and CEPT modes. The CNUCLB mode loops received system time slot X back to the system in time slot 0. The selected time slot is not routed through the receive elastic store buffer and, therefore, will not be affected by systemAIS, RLFA conditions, or controlled slips. Any time slot can be looped back to the system. Time slot X transmitted to the line is not affected by this loopback mode. Looping received system time slot 0 has no effect on time slot 0 transmitted to the line, i.e., the transmit framer will always overwrite the FAS and NOT FAS data in time slot 0 transmitted to the line. This mode can be selected by setting register FRM_PR24 to 110A4A3A2A1A0 and register FRM_PR10 bit 3 to 1, where A4A3A2A1A0 is the binary address of the selected time slot.
The loopback and transmission modes are described in detail below:
s
The LLB mode loops the receive line data and clock back to the transmit line. The received data is processed by the receive framer and transmitted to the system interface. This mode can be selected by setting register FRM_PR24 to 001xxxxx (binary). The BLB mode loops the receive system data back to the system after: -- The transmit framer processes the data, and -- The receive framer processes the data.
s
In the BLB mode, AIS is always transmitted to the line interface. This mode can be selected by setting register FRM_PR24 to 010xxxxx (binary).
s
s
The STSSLB mode loops one and only one received system time slot back to the transmit system interface. The selected looped back time-slot data is not processed by either the transmit framer or the receive framer. The selected time slot does not pass through the receive elastic store buffer and therefore will not be affected by system-AIS, RLFA conditions, or controlled slips events. Once selected, the desired time-slot position has the programmable idle code in register FRM_PR22 transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback. This mode can be selected by setting register FRM_PR24 to 011A4A3A2A1A0, where A4A3A2A1A0 is the binary address of the selected time slot.
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Preliminary Data Sheet October 2000
Alarms and Performance Monitoring (continued)
Secondary Loopback Modes There are two secondary loopback modes supported:
s s
Secondary-single time-slot system loopback (S-STSSLB). Secondary-single time-slot line loopback (S-STSLLB).
The loopbacks are described in detail below:
s
The secondary-STSSLB mode loops one and only one received system time slot back to the transmit system interface. The selected time-slot data looped back is not processed by either the transmit framer or the receive framer. The selected time slot does not pass through the receive elastic store buffer and therefore will not be affected by system-AIS, RLFA conditions, or controlled slips events. Whenever the secondary loopback register is programmed to the same time slot as the primary register, the primary loopback mode will control that time slot. Once selected, the desired time-slot position has the programmable line idle code in register FRM_PR22 transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback. The secondary-STSLLB mode loops one and only one line time slot back to the line. The selected time slot data is looped to the line after being processed by the receive framer and it passes through the receive elastic store. The selected time slot has the programmable idle code in register FRM_PR22 transmitted to the system interface one frame before implementing the loopback and for the duration of the loopback. In CEPT, selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will not be looped back to the line and should not be chosen in this mode).
s
Table 33 defines the deactivation of the two secondary loopback modes as a function of the activation of the primary loopback and test transmission modes. Table 33. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function of Activating the Primary Loopback Modes Primary Loopback Mode STSSLB STSLLB BLB CNUBT LLB NUCLB PLLB Deactivation of S-STSSLB If primary time slot = secondary If primary time slot = secondary Always If the secondary time slot is TS0 or if the primary time slot = secondary Always If the secondary time slot is TS0 or if the primary time slot = secondary Always Deactivation of S-STSLLB If primary time slot = secondary If primary time slot = secondary Always If primary time slot = secondary Always If primary time slot = secondary Always
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Alarms and Performance Monitoring (continued)
Figure 28 illustrates the various loopback modes implemented by each framer unit.
FRAMER SYSTEM ES
RECEIVE SYSTEM DATA IS IGNORED LINE SYSTEM
AIS LINE
(1) LINE LOOPBACK TRANSMIT PROGRAMMABLE LINE IDLE CODE IN REGISTER FRM_PR22 IN OUTGOING LINE TS-X FRAMER LINE ES SYSTEM LOOPBACK TS-X LINE
(2) BOARD LOOPBACK TRANSMIT PROGRAMMABLE IDLE CODE IN REGISTER FRM_PR22 IN OUTGOING SYSTEM TS-X INSERT ONLY TIME SLOT X SYSTEM ES
(3) SINGLE TIME-SLOT SYSTEM LOOPBACK
(4) SINGLE TIME-SLOT LINE LOOPBACK
FRAMER LINE ES SYSTEM LINE
TRANSMIT FRAMER
SYSTEM
TRANSMIT LINE TS-X IN SYSTEM TS-X AND SYSTEM TS-0 (5) CEPT NAILED-UP BROADCAST TRANSMISSION FRAMER LINE ES LOOPBACK TS-X IN TS-0
(6) PAYLOAD LINE LOOPBACK
SYSTEM
(7) CEPT NAILED-UP CONNECT LOOPBACK
5-3914(F).d
Figure 28. Loopback and Test Transmission Modes
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Preliminary Data Sheet October 2000
Alarms and Performance Monitoring (continued)
Line Test Patterns
Test patterns may be transmitted to the line through either register FRM_PR20 or register FRM_PR69. Only one of these sources may be active at the same time. Signaling must be inhibited while sending these test patterns. Transmit Line Test Patterns--Using Register FRM_PR20 The transmit framer can be programmed through register FRM_PR20 to transmit various test patterns. These test patterns, when enabled, overwrite the received CHI data. The test patterns available using register FRM_PR20 are:
s
The unframed-AIS pattern which consists of a continuous bit stream of ones (. . . 111111 . . .) enabled by setting register FRM_PR20 bit 0 to 1. The unframed-auxiliary pattern which consists of a continuous bit stream of alternating ones and 0s (. . . 10101010 . . .) enabled by setting register FRM_PR20 bit 1 to 1. The quasi-random test signal, enabled by setting register FRM_PR20 bit 3 to 1, which consists of the following: -- A pattern produced by means of a 20-stage shift register with feedback taken from the seventeenth and twentieth stages via an exclusive-OR gate to the first stage. The output is taken from the twentieth stage and is forced to a 1 state whenever the next 14 stages (19 through 6) are all 0. The pattern length is 1,048,575 or 220 - 1 bits. This pattern is described in detail in AT&T Technical Reference 62411 [5] Appendix and illustrated in Figure 29. -- Valid framing bits. -- Valid transmit facility data link (TFDL) bit information. -- Valid CRC bits.
s
s
A B
C XOR
D #1
D #2 D-TYPE FLIP-FLOPS
D #17
D #18
D #19
D #20
#6 #19 NOR #20
QUASI-RANDOM TEST OUTPUT
OR
5-3915(F).dr.1
Figure 29. 20-Stage Shift Register Used to Generate the Quasi-Random Signal
s
The pseudorandom test pattern, enabled by setting register FRM_PR20 bit 2 to 1, which consists of: -- A 215- 1 pattern inserted in the entire payload (time slots 1--24 in DS1 and time slots 1--32 in CEPT), as described by ITU Rec. 0.151 and illustrated in Figure 30. -- Valid framing pattern. -- Valid transmit facility data link (TFDL) bit data. -- Valid CRC bits.
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TFRA08C13 OCTAL T1/E1 Framer
Alarms and Performance Monitoring (continued)
A B
C
D #1
D #2
D #3
D #13
D #14
D PSEUDORANDOM #15 TEST OUTPUT
XOR
D-TYPE FLIP-FLOPS
5-3915(F).er.1
Figure 30. 15-Stage Shift Register Used to Generate the Pseudorandom Signal The idle code test pattern, enabled by setting register FRM_PR20 bit 6 to 1, which consists of the following: -- The programmable idle code, programmed through register FRM_PR22, in time slots 1--24 in DS1 and 0--31 in CEPT. -- Valid framing pattern. -- Valid transmit facility data link (TFDL) bit data. -- Valid CRC bits.
s
Transmit Line Test Patterns--Using Register FRM_PR69 Framed or unframed patterns indicated in Table 34 may be generated and sent to the line by register FRM_PR69 and by setting register FRM_PR20 to 00 (hex). Selection of transmission of either a framed or unframed test pattern is made through FRM_PR69 bit 3. If one of the test patterns of register FRM_PR69 is enabled, a single bit error can be inserted into the transmitted test pattern by toggling register FRM_PR69 bit 1 from 0 to 1. Table 34. Register FRM_PR69 Test Patterns Pattern Register FRM_PR69 Bit 7 Bit 6 MARK (all ones AIS) QRSS (2 2 -1 63 (26 - 1) - 1) - 1) reversed
11 5 20
Bit 5 0 0 1 1 0 0 1 1 0 0 1 1 0
Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1
- 1 with zero suppression)
511 511
(29 (29
2047 (211 - 1) 2047 (2 2
15
- 1) reversed
-1 -1 -1 -1
220 220 223
1:1 (alternating)
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Alarms and Performance Monitoring (continued)
Receive Line Pattern Monitor--Using Register FRM_SR7
The receive framer pattern monitor continuously monitors the received line, detects the following fixed framed patterns, and indicates detection in register FRM_SR7 bit 6 and bit 7.
s
The pseudorandom test pattern as described by ITU Rec. O.151 and illustrated in Figure 30. Detection of the pattern is indicated by register FRM_SR7 bit 6 = 1. The quasi-random test pattern described in AT&T Technical Reference 62411[5] Appendix and illustrated in Figure 29. Detection of the pattern is indicated by register FRM_SR7 bit 7 = 1.
s
In DS1 mode, the received 193 bit frame must consist of 192 bits of pattern plus 1 bit of framing information. In CEPT mode, the received 256 bit frame must consist of 248 bits of pattern plus 8 bits (TS0) of framing information. No signaling, robbed bit in the case of T1 and TS16 signaling in the case of CEPT, may be present for successful detection of these two test patterns. To establish lock to the pattern, 256 sequential bits must be received without error. When lock to the pattern is achieved, the appropriate bit of register FRM_SR7 is set to a 1. Once pattern lock is established, the monitor can withstand up to 32 single bit errors per frame without a loss of lock. Lock will be lost if more than 32 errors occur within a single frame. When such a condition occurs, the appropriate bit of register FRM_SR7 is deasserted. The monitor then resumes scanning for pattern candidates. Receive Line Pattern Detector--Using Register FRM_PR70 Framed or unframed patterns indicated in Table 35 may be detected using register FRM_PR70. Detection of the selected test pattern is indicated when register FRM_SR7 bit 4 is set to 1. Selection of a framed or unframed test pattern is made through FRM_PR70 bit 3. Bit errors in the received test pattern are indicated when register FRM_SR7 bit 5 = 1. The bit errors are counted and reported in registers FRM_SR8 and FRM_SR9, which are normally the BPV counter registers. (In this test mode, the BPV counter registers do not count BPVs but count only bit errors in the received test pattern.) Table 35. Register FRM_PR70 Test Patterns Pattern Register FRM_PR70 Bit 7 Bit 6 MARK (all ones AIS) QRSS 25 63 -1 (26 - 1)
9
Bit 5 0 0 1 1 0 0 1 1 0 0 1 1 0
Bit 4 0 1 0 1 0 1 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1
(220
- 1 with zero suppression)
511 (29 - 1) 511 (2 - 1) reversed 2047 (2 2047 215 220 220 2
23 11
- 1) - 1) reversed
(211
-1 -1 -1 -1
1:1 (alternating)
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Alarms and Performance Monitoring (continued)
The pattern detector continuously monitors the received line for the particular pattern selected in register FRM_PR70 bit 7--bit 4 (DPTRN). To establish detector lock to the pattern, 256 sequential bits must be detected. Once the detector has locked onto the selected pattern, it will remain locked to the established alignment and count all unexpected bits as single bit errors until register FRM_PR70 bit 2 (DBLKSEL) is set to 0. To select a pattern or change the pattern to be detected, the following programming sequence must be followed:
s s s
DBLKSEL (register FRM_PR70 bit 2) is set to 0. The new pattern to be detected is selected by setting register FRM_PR70 bit 7--bit 4 to the desired value. DBLKSEL (register FRM_PR70 bit 2) is set to 1.
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Alarms and Performance Monitoring (continued)
Automatic and On-Demand Commands
Various alarms can be transmitted either automatically as a result of various alarm conditions or on demand. After reset, all automatic transmissions are disabled. The user can enable the automatic or on-demand actions by setting the proper bits in the automatic and on-demand action registers as identified below in Table 36. Table 37 shows the programmable automatically transmitted signals and the triggering mechanisms for each. Table 37 shows the on-demand commands. Table 36. Automatic Enable Commands Action Transmit Remote Frame Alarm (RFA) Trigger Loss of frame alignment (RLFA) Loss of CEPT time slot 16 multiframe alignment (RTS16LMFA) Loss of CEPT time slot 0 multiframe alignment (RTS0LMFA) Detection of the timer (100 ms or 400 ms) expiration due to loss of CEPT multiframe alignment Detection of the CEPT RSa6 = 8 (hex) code Detection of the CEPT RSa6 = C (hex) code Detection of CEPT CRC-4 error RTS0LMFA Detection of the timer (100 ms or 400 ms) expiration due to loss of CEPT multiframe alignment RLFA Detection of the timer (100 ms or 400 ms) expiration due to loss of CEPT multiframe alignment RTS16LMFA Enabling Register Bit FRM_PR27 bit 0 = 1 FRM_PR27 bit 1 = 1 FRM_PR27 bit 2 = 1 FRM_PR27 bit 3 = 1 FRM_PR9 bit 7--bit 0 = 0xxxx1x1 or 0xxx1xx1 FRM_PR27 bit 4 = 1 FRM_PR27 bit 5 = 1 FRM_PR28 bit 3 = 1 FRM_PR28 bit 4 = 1 FRM_PR28 bit 5 = 1 FRM_PR9 bit 7--bit 0 = 0xxxx1x1 or 0xxx1xx1 FRM_PR19 bit 0 = 1 FRM_PR19 bit 1 = 1 FRM_PR9 bit 7--bit 0 = 0xxxx1x1 or 0xxx1xx1 FRM_PR41 bit 4 = 1
Transmit CEPT E Bit = 0
Transmit AIS to System
Transmit CEPT Time Slot 16 Remote Multiframe Alarm to Line Transmit CEPT AIS in Time Slot 16 to System Automatic Enabling of DS1 Line Loopback On/Off Automatic Enabling of ESF FDL Line Loopback On/Off Automatic Enabling of ESF FDL Payload Loopback On/Off
RTS16LMFA Line loopback on/off code ESF line loopback on/off code ESF payload loopback on/off code
FRM_PR44 bit 6 = 1 FRM_PR19 bit 4 = 1 FRM_PR19 bit 6 = 1 FRM_PR19 bit 7 = 1
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TFRA08C13 OCTAL T1/E1 Framer
Alarms and Performance Monitoring (continued)
Table 37. On-Demand Commands Type Frame Format D4 (US) DDS ESF CEPT Transmit Time Slot 16 Remote CEPT Multiframe Alarm to the Line Transmit Data Link AIS (Squelch) Transmit Line Test Patterns Action Bit 2 of all time slots = 0 Bit 6 in time slot 24 = 0 Pattern of 1111111100000000 in the FDL F-bit position A bit = 1 Time slot 16 remote alarm bit = 1 Transmit data link bit = 1 Transmit test patterns to the line interface FRM_PR41 bit 5 = 1 FRM_PR21 bit 4 = 1 See Transmit Line Test Patterns--Using Register FRM_PR20 section on page 78 and Transmit Line Test Patterns--Using Register FRM_PR69 section on page 79. FRM_PR19 bit 3 = 1 FRM_PR44 bit 1 = 1 Enabling Register Bit FRM_PR27 bit 6 = 1 FRM_PR27 bit 7 = 1
Transmit Remote Frame Alarm D4 (Japanese) FS bit in frame 12 = 1
SLC-96, ESF
All
Transmit System AIS
All
Transmits AIS to the system Transmit ABCD = 1111 to the system Suspend the updating of the receive signaling registers Transmit AIS in time slot 16 to the line
Transmit System Signaling AIS T1 (Squelch) CEPT Receive Signaling Inhibit Receive Framer Reframe Transmit Line Time Slot 16 Enable Loopback All All CEPT All
Transmit AIS in system time slot 16 FRM_PR44 bit 7 = 1 FRM_PR44 bit 3 = 1
Force the receive framer to reframe FRM_PR26 bit 2 = 1 FRM_PR41 bit 6 = 1
Enables system and line loopbacks See Loopback and Transmission Modes section on page 75. The framer and FDL are placed in FRM_PR26 bit 0 = 1 the reset state for four RCLK clock cycles. The framer parameter registers are forced to the default value. The framer and FDL are placed in FRM_PR26 bit 1 = 1 the reset state as long as this bit is set to 1. The framer parameter registers are not changed from their programmed values.
Framer Software Reset
All
Framer Software Restart
All
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Facility Data Link
Data may be extracted from and inserted into the facility data link in SLC-96, DDS, ESF, and CEPT framing formats. In CEPT, any one of the Sa bits can be declared as the facility data link by programming register FRM_PR43 bit 0--bit 2. Access to the FDL is made through:
s s
The FDL pins (RFDL, RFDLCK, TFDL, and TFDLCK). Figure 15 shows the timing of these signals. The 64-byte FIFO of the FDL HDLC block. FDL information passing through the FDL HDLC Section may be framed in HDLC format or passed through transparently.
t8 TFDLCK t8: TFDLCK CYCLE = 125 s (DDS) 250 s (ALL OTHER MODES) t9 t9
TFDL
t9: TFDL TO TFDLCK SETUP/HOLD = 40 ns
t10
RFDLCK
t10: RFDLCK CYCLE = 125 s (DDS) 250 s (ALL OTHER MODES)
t11 RFDL
t11: RFDLCK TO RFDL DELAY = 40 ns
5-3910(F).cr.1
Figure 31. TFRA08C13 Facility Data Link Access Timing of the Transmit and Receive Framer Sections In the ESF frame format, automatic assembly and transmission of the performance report message (PRM) as defined in both ANSI T1.403-1995 and Telcordia Technologies* TR-TSY-000194 Issue 1, 12--87 is managed by the receive framer and transmit FDL sections. The ANSI T1.403-1995 bit-oriented data link messages (BOM) can be transmitted by the transmit FDL section and recognized and stored by the receive FDL section. writing to register FDL_PR0 bit 4-- bit 7. When a valid ANSI code is detected, register FDL_SR0 bit 7 (FRANSI) is set.
s
HDLC operation. This is the default mode of operation when the FDL receiver is enabled (register FDL_PR1 bit 2 = 1). The HDLC framer detects the HDLC flags, checks the CRC bytes, and stores the data in the FDL receiver FIFO (register FDL_SR4) along with a status of frame (SF) byte. HDLC operation with performance report messages (PRM). This mode is enabled by setting register FDL_PR1 bit 2 and bit 6 to 1. In this case, the receive FDL will store the 13 bytes of the PRM report field in the FDL receive FIFO (register FDL_SR4) along with a status of frame (SF) byte. Transparent operation. Enabling the FDL and setting register FDL_PR9 bit 6 (FTM) to 1 disables the HDLC processing. Incoming data link bits are stored in the FDL receive FIFO (register FDL_SR4).
s
Receive Facility Data Link Interface
Summary A brief summary of the receive facility data link functions is given below:
s
s
Bit-oriented message (BOM) operation. The ANSI T1.403-1995 bit-oriented data link messages are recognized and stored in register FDL_SR3. The number of times that an ANSI code must be received for detection can be programmed from 1 to 10 by
* Telcordia Technologies is a registered trademark of Bell
Communications Research, Inc.
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TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link (continued)
s
Transparent operation with pattern match. Enabling the FDL and setting registers FDL_PR9 bit 5 (FMATCH) and FDL_PR9 bit 6 (FTM) to 1 forces the FDL to start storing data in the FDL receive FIFO (register FDL_SR4) only after the programmable match character defined in register FDL_PR8 bit 0--bit 7 has been detected. The match character and all subsequent bytes are placed into the FDL receive FIFO.
The FDL interface to the receive framer is illustrated in Figure 32.
RECEIVE LINE DATA
LOSS OF FRAME ALIGNMENT RECEIVE FRAMER
RECEIVE FDL DATA EXTRACTER RFDL RFDLCK RFDL RECEIVE FACILITY DATA RECEIVE FACILITY DATA LINK HDLC
TRANSPARENT RFDLCK
ANSI T1.403-1995 BIT-ORIENTED DATA LINK MESSAGES MONITOR
ONE 8-bit REGISTER IDENTIFYING THE ESF BIT-ORIENTED CODE
RECEIVE FACILITY DATA LINK FIFO 64 8-bit LOCATIONS
MICROPROCESSOR INTERFACE
5-4560(F).ar.1
Figure 32. Block Diagram for the Receive Facility Data Link Interface Receive ANSI T1.403 Bit-Oriented Messages (BOM)
s
The receive FDL monitor will detect any of the ANSI T1.403 ESF bit-oriented messages (BOMs) and generate an interrupt, enabled by register FDL_PR6 bit 7, upon detection. Register FDL_SR0 bit 7 (FRANSI) is set to 1 upon detection of a valid BOM and then cleared when read. The received ESF FDL bit-oriented messages are received in the form 111111110X0X1X2X3X4X50 (the left most bit is received first). The bits designated as X are the defined ANSI ESF FDL code bits. These code bits are written into the received ANSI FDL status register FDL_SR3 when the entire code is received. The minimum number of times a valid code must be received before it is reported can be programmed from 1 to 10 using register FDL_PR0 bit 4--bit 7.
s
s
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Facility Data Link (continued)
The received ANSI FDL status byte, register FDL_SR3, has the following format. Table 38. Receive ANSI Code B7 0 B6 0 B5 X5 B4 X4 B3 X3 B2 X2 B1 X1 B0 X0
Receive ANSI Performance Report Messages (PRM) As defined in ANSI T1.403, the performance report messages consist of 15 bytes, starting and ending with an HDLC flag. The receive framer status information consists of four pairs of octets, as shown in Table 39. Upon detection of the PRM message, the receive FDL extracts the 13 bytes of the PRM report field and stores it in the receive FDL FIFO along with the status of frame byte. Table 39. Performance Report Message Structure* Octet PRM B7 PRM B6 PRM B5 PRM B4 PRM B3 PRM B2 PRM B1 PRM B0 Number 1 2 3 4 5 6 7 8 9 10 11 12 13--14 15 Flag SAPI TEI Control U1 U2 G1 R U1 U2 G1 R U1 U2 G1 R U1 U2 G1 R FCS Flag C/R EA EA G6 Nl G6 Nl G6 Nl G6 Nl
G3 FE G3 FE G3 FE G3 FE
LV SE LV SE LV SE LV SE
G4 LB G4 LB G4 LB G4 LB
G5 G2 G5 G2 G5 G2 G5 G2
SL Nm SL Nm SL Nm SL Nm
* The rightmost bit (bit 1) is transmitted first for all fields except for the 2 bytes of the FCS that are transmitted left most bit (bit 8) first.
The definition of each PRM field is shown in Table 40, and octet content is shown in Table 41.
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TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link (continued)
Table 40. FDL Performance Report Message Field Definition PRM Field Definition
G1 = 1 CRC Error Event = 1 G2 = 1 1 < CRC Error Event 5 G3 = 1 5 < CRC Error Event 10 G4 = 1 10 < CRC Error Event 100 G5 = 1 100 < CRC Error Event 319 G6 = 1 CRC Error Event 320 SE = 1 Severely Errored Framing Event 1 (FE will = 0) FE =1 Frame Synchronization Bit Error Event 1 (SE will = 0) LV = 1 Line Code Violation Event 1 SL = 1 Slip Event 1 LB = 1 Payload Loopback Activated U1, U2 = 0 Reserved R=0 Reserved (default value = 0) Nm, Nl = 00, One-Second Report Modulo 4 Counter 01, 10, 11 Table 41. Octet Contents and Definition Octet Number 1 2 3 4 5, 6 7, 8 9, 10 11, 12 13, 14 15 Octet Contents 01111110 00111000 00111010 00000001 00000011 Variable Variable Variable Variable Variable 01111110 Definition Opening LAPD Flag From CI: SAPI = 14, C/R = 0, EA = 0 From Carrier: SAPI = 14, C/R = 1, EA = 0 TEI = 0, EA = 1 Unacknowledged Frame Data for Latest Second (T) Data for Previous Second (T - 1) Data for Earlier Second (T - 2) Data for Earlier Second (T - 3) CRC-16 Frame Check Sequence Closing LAPD Flag
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Facility Data Link (continued)
Receive HDLC Mode This is the default mode of the FDL. The receive FDL receives serial data from the receive framer, identifies HDLC frames, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive FIFO. The receive queue manager forms a status of frame (SF) byte for each HDLC frame and stores the SF byte in the receive FDL FIFO (register FDL_SR4) after the last data byte of the associated frame. HDLC frames consisting of n bytes will have n + 1 bytes stored in the receive FIFO. The frame check sequence bytes (CRC) of the received HDLC frame are not stored in the receive FIFO. When receiving ANSI PRM frames, the frame check sequence bytes are stored in the receive FIFO. The SF byte has the following format. Table 42. Receive Status of Frame Byte RSF B7 BAD CRC RSF B6 ABORT RSF B5 RFIFO OVERRUN RSF B4 BAD BYTE COUNT RSF B3 0 RSF B2 0 RSF B1 0 RSF B0 0
Bit 7 of the SF status byte is the CRC status bit. A 1 indicates that an incorrect CRC was detected. A 0 indicates the CRC is correct. Bit 6 of the SF status byte is the abort status. A 1 indicates the frame associated with this status byte was aborted (i.e., the abort sequence was detected after an opening flag and before a subsequent closing flag). An abort can also cause bits 7 and/or 4 to be set to 1. An abort is not reported when a flag is followed by seven ones. Bit 5 is the FIFO overrun bit. A 1 indicates that a receive FIFO overrun occurred (the 64-byte FIFO size was exceeded). Bit 4 is the FIFO bad byte count that indicates whether or not the bit count received was a multiple of eight (i.e., an integer number of bytes). A 1 indicates that the bit count received after 0-bit deletion was not a multiple of eight, and a 0 indicates that the bit count was a multiple of eight. When a non-byte-aligned frame is received, all bits received are present in the receive FIFO. The byte before the SF status byte contains less than eight valid data bits. The HDLC block provides no indication of how many of the bits in the byte are valid. User application programming controls processing of non-byte-aligned frames. Bit 3--bit 0 of the SF status byte are not used and are set to 0. A good frame is implied when the SF status byte is 00 (hex). Receive FDL FIFO Whenever an SF byte is present in the receive FIFO, the end of frame registers FDL_SR0 bit 4 (FREOF) and FDL_SR2 bit 7 (FEOF) bits are set. The receiver queue status (register FDL_SR2 bit 0--bit 6) bits report the number of bytes up to and including the first SF byte. If no SF byte is present in the receive FIFO, the count directly reflects the number of data bytes available to be read. Depending on the FDL frame size, it is possible for multiple frames to be present in the receive FIFO. The receive fill level indicator register FDL_PR6 bit 0--bit 5 (FRIL) can be programmed to tailor the service time interval to the system. The receive FIFO full register FDL_SR0 bit 3 (FRF) interrupt is set in the interrupt status register when the receive FIFO reaches the preprogrammed full position. An FREOF interrupt is also issued when the receiver has identified the end of frame and has written the SF byte for that frame. An FDL overrun interrupt register FDL_SR0 bit 5 (FROVERUN) is generated when the receiver needs to write either status or data to the receive FIFO while the receive FIFO is full. An overrun condition will cause the last byte of the receive FIFO to be overwritten with an SF byte indicating the overrun status. A receive idle register FDL_SR0 bit 6 (FRIDL) interrupt is issued whenever 15 or more continuous ones have been detected.
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TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link (continued)
The receive queue status bits, register FDL_SR2 bit 0--bit 6 (FRQS), are updated as bytes are loaded into the receive FIFO. The SF status byte is included in the byte count. When the first SF status byte is placed in the FIFO, register FDL_SR0 bit 4 (FREOF) is set to 1, and the status freezes until the FIFO is read. As bytes are read from the FIFO, the queue status decrements until it reads 1. The byte read when register FDL_SR2 bit 0--bit 6 = 0000001 and the FREOF bit is 1 is the SF status byte describing the error status of the frame just read. Once the first SF status byte is read from the FIFO, the FIFO status is updated to report the number of bytes to the next SF status byte, if any, or the number of additional bytes present. When FREOF is 0, no SF status byte is currently present in the FIFO, and the FRQS bits report the number of bytes present. As bytes are read from the FIFO, the queue status decrements with each read until it reads 0 when the FIFO is totally empty. The FREOF bit is also 0 when the FIFO is completely empty. Thus, the FRQS and FREOF bit provide a mechanism to recognize the end of 1 frame and the beginning of another. Reading the FDL receiver status register does not affect the FIFO buffers. In the event of a receiver overrun, an SF status byte is written to the receive FIFO. Multiple SF status bytes can be present in the FIFO. The FRQS reports only the number of bytes to the first SF status byte. If FRQS is 0, do not read the receive FIFO. A read will result in the corruption of receive FIFO. To allow users to tailor receiver FIFO service intervals to their systems, the receiver interrupt level bits in register FDL_PR6 bit 0--bit 5 (FRIL) are provided. These bits are coded in binary and determine when the receiver full interrupt, register FDL_SR0 bit 3 (FRF), is asserted. The interrupt pin transition can be masked by setting register FDL_PR2 bit 3 (FRFIE) to 0. The value programmed in the FRIL bits equals the total number of bytes necessary to be present in the FIFO to trigger an FRF interrupt. The FRF interrupt alone is not sufficient to determine the number of bytes to read, since some of the bytes may be SF status bytes. The FRQS bits
and FREOF bit allow the user to determine the number of bytes to read. The FREOF interrupt can be the only interrupt for the final frame of a group of frames, since the number of bytes received to the end of the frame cannot be sufficient to trigger an FRF interrupt. Programming Note: Since the receiver writing to the receive FIFO and the host reading from the receive FIFO are asynchronous events, it is possible for a host read to put the number of bytes in the receive FIFO just below the programmed FRIL level and a receiver write to put it back above the FRIL level. This causes a new FRF interrupt, and has the potential to cause software problems. It is recommended that during service of the FRF interrupt, the FRF interrupt be masked FRFIE = 0, and the interrupt register be read at the end of the service routine, discarding any FRF interrupt seen, before unmasking the FRF interrupt. Receiver Overrun A receiver overrun occurs if the 64-byte limit of the receiver FIFO is exceeded, i.e., data has been received faster than it has been read out of the receive FIFO. Upon overrun, an SF status byte with the overrun bit (bit 5) set to 1 replaces the last byte in the FIFO. The SF status byte can have other error conditions present. For example, it is unlikely the CRC is correct. Thus, care should be taken to prioritize the possible frame errors in the software service routine. The last byte in the FIFO is overwritten with the SF status byte regardless of the type of byte (data or SF status) being overwritten. The overrun condition is reported in register FDL_SR0 bit 5 and causes the interrupt pin to be asserted if it is not masked (register FDL_PR2 bit 5 (FROVIE)). Data is ignored until the condition is cleared and a new frame begins. The overrun condition is cleared by reading register FDL_SR0 bit 5 and reading at least 1 byte from the receive FIFO. Because multiple frames can be present in the FIFO, good frames as well as the overrun frame can be present. The host can determine the overrun frame by looking at the SF status byte.
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Facility Data Link (continued)
Transmit Facility Data Link Interface
The FDL interface of the transmit framer is shown in Figure 33, indicating the priority of the FDL sources. The remote frame alarm, enabled using register FRM_PR27, is given the highest transmission priority by the transmit framer. The ANSI T1.403-1995 bit-oriented data link message transmission is given priority over performance report messages and the automatic transmission of the performance report messages is given priority over FDL HDLC transmission. Idle code is generated by the FDL unit when no other transmission is enabled. The FDL transmitter is enabled by setting register FDL_PR1 bit 3 to 1.
MICROPROCESSOR INTERFACE
TRANSMIT FDL FIFO TRANSPARENT
RECEIVE FRAMER
TRANSMIT FDL HDLC FRAMER
TRANSMIT PERFORMANCE REPORT MESSAGE ASSEMBLER
TFDL
TRANSMIT ANSI T1.403 FDL BIT CODE GENERATOR
FDL IDLE CODE GENERATOR FDL YELLOW ALARM
TFDLCK
TRANSMIT FDL CLOCK GENERATOR
TFDLCK
TRANSMIT FRAME ASSEMBLER
5-4561(F).a
Figure 33. Block Diagram for the Transmit Facility Data Link Interface Transmit ANSI T1.403 Bit-Oriented Messages (BOM) When the ANSI BOM mode is enabled by setting register FDL_PR10 bit 7 to 1, the transmit FDL can send any of the ANSI T1.403 ESF bit-oriented messages automatically through the FDL bit in the frame. The transmit ESF FDL bit-oriented messages of the form 111111110X0X1X2X3X4X50 are taken from the transmit ANSI FDL parameter register FDL_PR10 bit 0--bit 5. The ESF FDL bit-oriented messages will be repeated while register FDL_PR10 bit 7 (FTANSI) is set to 1.
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TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link (continued)
Transmit ANSI Performance Report Messages (PRM) When the ANSI PRM mode is enabled by setting register FDL_PR1 bit 7 to 1, the transmit FDL assembles and transmits the ANSI performance report message once every second. After assembling the ANSI PRM message, the receive framer stores the current second of the message in registers FRM_SR62 and FRM_SR63 and transfers the data to the FDL transmit FIFO. After accumulating three seconds (8 bytes) of the message, the FDL transmit block appends the header and the trailer (including the opening and closing flags) to the PRM messages and transmits it to the framer for transmission to the line. Table 39--Table 41 show the complete format of the PRM HDLC packet.
HDLC Operation
HDLC operation is the default mode of operation. The transmitter accepts parallel data from the transmit FIFO, converts it to a serial bit stream, provides bit stuffing as necessary, adds the CRC-16 and the opening and closing flags, and sends the framed serial bit stream to the transmit framer. HDLC frames on the serial link have the following format. Table 43. HDLC Frame Format Opening Flag 01111110 User Data Field 8 bits Frame Check Sequence (CRC) 16 bits Closing Flag 01111110
All bits between the opening flag and the CRC are considered user data bits. User data bits such as the address, control, and information fields for LAPB or LAPD frames are fetched from the transmit FIFO for transmission. The 16 bits preceding the closing flag are the frame check sequence, cyclic redundancy check (CRC), bits. Zero-Bit Insertion/Deletion (Bit Stuffing/Destuffing) The HDLC protocol recognizes three special bit patterns: lags, aborts, and idles. These patterns have the common characteristic of containing at least six consecutive ones. A user data byte can contain one of these special patterns. Transmitter zero-bit stuffing is done on user data and CRC fields of the frame to avoid transmitting one of these special patterns. Whenever five ones occur between flags, a 0 bit is automatically inserted after the fifth 1, prior to transmission of the next bit. On the receive side, if five successive ones are detected followed by a 0, the 0 is assumed to have been inserted and is deleted (bit destuffing).
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When receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by seven consecutive ones. The receive FDL unit will abort a frame whenever the receive framer detects a loss of frame alignment. This results in the abort bit, and possibly the bad byte count bit and/or bad CRC bits, being set in the status of frame status byte (see Table 42) which is appended to the receive data queue. All subsequent bytes are ignored until a valid opening flag is received. Idles In accordance with the HDLC protocol, the HDLC block recognizes 15 or more contiguous received ones as idle. When the HDLC block receives 15 contiguous ones, the receiver idle bit register FDL_SR0 bit 6 (RIDL) is set. For transmission, the ones idle byte is defined as the binary pattern 11111111 (FF (hex)). If the FLAGS control bit in register FDL_PR0 bit 1 is 0, the ones idle byte is sent as the time-fill byte between frames. A time-fill byte is sent when the transmit FIFO is empty and the transmitter has completed transmission of all previous frames. Frames are sent back-to-back otherwise. CRC-16 For given user data bits, 16 additional bits that constitute an error-detecting code (CRC-16) are added by the transmitter. As called for in the HDLC protocol, the frame check sequence bits are transmitted most significant bit first and are bit stuffed. The cyclic redundancy check (or frame check sequence) is calculated as a function of the transmitted bits by using the ITU-T standard polynomial: x 16 + x 12 + x 5 + 1 The transmitter can be instructed to transmit a corrupted CRC by setting register FDL_PR2 bit 7 (FTBCRC) to 1. As long as the FTBCRC bit is set, the CRC is corrupted for each frame transmitted by logically flipping the least significant bit of the transmitted CRC. The receiver performs the same calculation on the received bits after destuffing and compares the results to the received CRC-16 bits. An error indication occurs if, and only if, there is a mismatch.
Facility Data Link (continued)
Flags* All flags have the bit pattern 01111110 and are used for frame synchronization. The FDL HDLC block automatically sends two flags between frames. If the chip-configuration register FDL_PR0 bit 1 (FLAGS) is cleared to 0, the ones idle byte (11111111) is sent between frames if no data is present in the FIFO. If FLAGS is set to 1, the FDL HDLC block sends continuous flags when the transmit FIFO is empty. The FDL HDLC does not transmit consecutive frames with a shared flag; therefore, two successive flags will not share the intermediate 0. An opening flag is generated at the beginning of a frame (indicated by the presence of data in the transmit FIFO and the transmitter enable register FDL_PR1 bit 3 = 1). Data is transmitted per the HDLC protocol until a byte is read from the FIFO while register FDL_PR3 bit 7 (FTFC) set to 1. The FDL HDLC block follows this last user data byte with the CRC sequence and a closing flag. The receiver recognizes the 01111110 pattern as a flag. Two successive flags may or may not share the intermediate 0 bit and are identified as two flags (i.e., both 011111101111110 and 0111111001111110 are recognized as flags by the FDL HDLC block). When the second flag is identified, it is treated as the closing flag. As mentioned above, a flag sequence in the user data or CRC bits is prevented by zero-bit insertion and deletion. The HDLC receiver recognizes a single flag between frames as both a closing and opening flag. Aborts An abort is indicated by the bit pattern of the sequence 01111111. A frame can be aborted by writing a 1 to register FDL_PR3 bit 6 (FTABT). This causes the last byte written to the transmit FIFO to be replaced with the abort sequence upon transmission. Once a byte is tagged by a write to FTABT, it cannot be cleared by subsequent writes to register FDL_PR3. FTABT has higher priority than FDL transmit frame complete (FTFC), but FTABT and FTFC should never be set to 1 simultaneously since this causes the transmitter to enter an invalid state requiring a transmitter reset to clear. A frame should not be aborted in the very first byte following the opening flag. An easy way to avoid this situation is to first write a dummy byte into the queue and then write the abort command to the queue.
* Regardless of the time-fill byte used, there always is an opening and closing flag with each frame. Back-to-back frames are separated by two flags.
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TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link (continued)
Transmit FDL FIFO Transmit FDL data is loaded into the 64-byte transmit FIFO via the transmit FDL data register, FDL_PR4. The transmit FDL status register indicates how many additional bytes can be added to the transmit FIFO. The transmit FDL interrupt trigger level register FDL_PR3 bit 0--bit 5 (FTIL) can be programmed to tailor service time intervals to the system environment. The transmitter empty interrupt bit is set in the FDL interrupt status register FDL_SR0 bit 1 (FTEM) when the transmit FIFO has sufficient empty space to add the number of bytes specified in register FDL_PR3 bit 0--bit 5. There is no interrupt indicated for a transmitter overrun that is writing more data than empty spaces exist. Overrunning the transmitter causes the last valid data byte written to be repeatedly overwritten, resulting in missing data in the frame. Data associated with multiple frames can be written to the transmit FIFO by the controlling microprocessor. However, all frames must be explicitly tagged with a transmit frame complete, register FDL_PR3 bit 7 (FTFC), or a transmit abort, register FDL_PR3 bit 6 (FTABT). The FTFC is tagged onto the last byte of a frame written into the transmitter FIFO and instructs the transmitter to end the frame and attach the CRC and closing flag following the tagged byte. Once written, the FTFC cannot be changed by another write to register FDL_PR3. If FTFC is not written before the last data byte is read out for transmission, an underrun occurs (FDL_SR0 bit 2). When the transmitter has completed a frame, with a closing flag or an abort sequence, register FDL_SR0 bit 0 (FTDONE) is set to 1. An interrupt is generated if FDL_PR2 bit 0 (FTDIE) is set to 1. Sending 1-Byte Frames Sending 1-byte frames with an empty transmit FIFO is not recommended. If the FIFO is empty, writing two data bytes to the FIFO before setting FTFC provides a minimum of eight TFDLCK periods to set FTFC. When 1 byte is written to the FIFO, FTFC must be written within 1 TFDLCK period to guarantee that it is effective. Thus, 1-byte frames are subject to underrun aborts. One-byte frames cannot be aborted with FTABT. Placing the transmitter in ones-idle mode, register FDL_PR0 bit 1 (FLAGS) = 0, lessens the frequency of underruns. If the transmit FIFO is not empty, then 1-byte frames present no problems.
Transmitter Underrun After writing a byte to the transmit queue, the user has eight TFDLCK cycles in which to write the next byte before a transmitter underrun occurs. An underrun occurs when the transmitter has finished transmitting all the bytes in the queue, but the frame has not yet been closed by setting FTFC. When a transmitter underrun occurs, the abort sequence is sent at the end of the last valid byte transmitted. A FTDONE interrupt is generated, and the transmitter reports an underrun abort until the interrupt status register is read. Using the Transmitter Status and Fill Level The transmitter-interrupt level bits, register FDL_PR3 bit 0--bit 5, allow the user to instruct the FDL HDLC block to interrupt the host processor whenever the transmitter has a predetermined number of empty locations. The number of locations selected determines the time between transmitter empty, register FRM_SR0 bit 1 (FTEM), interrupts. The transmitter status bits, register FDL_SR1, report the number of empty locations in the FDL transmitter FIFO. The transmitter empty dynamic bit, register FDL_SR1 bit 7 (FTED), like the FTEM interrupt bit, is set to 1 when the number of empty locations is less than or equal to the programmed empty level. FTED returns to 0 when the transmitter is filled to above the programmed empty level. Polled interrupt systems can use FTED to determine when they can write to the FDL transmit FIFO.
Transparent Mode
The FDL HDLC block can be programmed to operate in the transparent mode by setting register FDL_PR9 bit 6 (FTRANS) to 1. In the transparent mode of operation, no HDLC processing is performed on user data. The transparent mode can be exited at any time by setting FDL_PR9 bit 6 (FTRANS) to 0. It is recommended that the transmitter be disabled when changing in and out of transparent mode. The transmitter should be reset by setting FDL_PR1 bit 5 (FTR) to 1 whenever the mode is changed.
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(FALOCT) bit is 0 (align to octet), or only on octet boundaries if FALOCT is set to 1. The octet boundary is aligned relative to the first RFDLCK after the receiver has been enabled. The matched character and all subsequent bytes are placed in the receive FIFO. An FDL receiver reset, register FDL_PR1 bit 4 (FRR) = 1, causes the receiver to realign to the match character if FMATCH is set to 1. The receiver full (FRF) and receiver overrun (FROVERUN) interrupts in register FDL_SR0 act as in the HDLC mode. The received end of frame (FREOF) and receiver idle (FRIDL) interrupts are not used in the transparent mode. The match status (FMSTAT) bit is set to 1 when the receiver match character is first recognized. If the FMATCH bit is 0, the FMSTAT (FDL_PR9 bit 3) bit is set to 1 automatically when the first bit is received, and the octet offset status bits (FDL_PR9 bit 0--bit 2) read 000. If the FMATCH bit is programmed to 1, the FMSTAT bit is set to 1 upon recognition of the first receiver match character, and the octet offset status bits indicate the offset relative to the octet boundary at which the receiver match character was recognized. The octet offset status bits have no meaning until the FMSTAT bit is set to 1. An octet offset of 111 indicates byte alignment. An interrupt for recognition of the match character can be generated by setting the FRIL level to 1. Since the matched character is the first byte written to the FIFO, the FRF interrupt occurs with the writing of the match character to the receive FIFO. The operation of the receiver in transparent mode is summarized in Table 44.
Facility Data Link (continued)
In the transmit direction, the FDL HDLC takes data from the transmit FIFO and transmits that data exactly bit-for-bit on the TFDL interface. Transmit data is octetaligned to the first TFDLCK after the transmitter has been enabled. The bits are transmitted least significant bit first. When there is no data in the transmit FIFO, the FDL HDLC either transmits all ones, or transmits the programmed HDLC transmitter idle character (register FDL_PR5) if register FDL_PR9 bit 6 (FMATCH) is set to 1. To cause the transmit idle character to be sent first, the character must be programmed before the transmitter is enabled. The transmitter empty interrupt, register FDL_SR0 bit 1 (FTEM), acts as in the HDLC mode. The transmitterdone interrupt, register FDL_SR0 bit 0 (FTDONE), is used to report an empty FDL transmit FIFO. The FTDONE interrupt thus provides a way to determine transmission end. Register FDL_SR0 bit 2 (FTUNDABT) interrupt is not active in the transparent mode. In the receive direction, the FDL HDLC block loads received data from the RFDL interface directly into the receive FIFO bit-for-bit. The data is assumed to be least significant bit first. If FMATCH register FDL_PR9 bit 6 is 0, the receiver begins loading data into the receive FIFO beginning with the first RFDLCK detected after the receiver has been enabled. If the FMATCH bit is set to 1, the receiver does not begin loading data into the FIFO until the receiver match character has been detected. The search for the receiver match character is in a sliding window fashion if register FDL_PR9 bit 4 Table 44. Receiver Operation in Transparent Mode FALOCT X 0 1 FMATCH 0 1 1
Receiver Operation Serial-to-parallel conversion begins with first RFDLCK after FRE, register FDL_PR1 bit 2, is set. Data loaded to receive FIFO immediately. Match user-defined character using sliding window. Byte aligns once character is recognized. No data to receive FIFO until match is detected. Match user-defined character, but only on octet boundary. Boundary based on first RFDLCK after FRE, register FDL_PR1 bit 2, set. No data to receive FIFO until match is detected.
Note: The match bit (FMATCH) affects both the transmitter and the receiver. Care should be taken to correctly program both the transmit idle character and the receive match character before setting FMATCH. If the transmit idle character is programmed to FF (hex), the FMATCH bit appears to affect only the receiver.
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TFRA08C13 OCTAL T1/E1 Framer
Facility Data Link (continued)
Diagnostic Modes
Loopbacks The serial link interface can operate in two diagnostic loopback modes: (1) local loopback and (2) remote loopback. The local loopback mode is selected when register FDL_PR1 bit 1 (FLLB) is set to 1. The remote loopback is selected when register FDL_PR1 bit 0 (FRLB) is set to 1. For normal traffic, i.e., to operate the transmitter and receiver independently, the FLLP bit and the FRLB bits should both be cleared to 0. Local and remote loopbacks cannot be enabled simultaneously. In the local loopback mode:
s s s s s s
TFDLCK clocks both the transmitter and the receiver. The transmitter and receiver must both be enabled. The transmitter output is internally connected to the receiver input. The TFDL is active. The RFDL input is ignored. The communication between the transmit and receive FIFO buffers and the microprocessor continues normally.
XMIT HDLC FDL BLOCK
XMIT FIFO
XMIT HDLC
FDL XMIT INTERFACE
TFDL TFDLCK
RCVR FIFO
RCVR HDLC
FDL RCVR INTERFACE RFDL
RFDLCK
RCVR HDLC FDL BLOCK
5-4562(F)r.2
Figure 34. Local Loopback Mode
In the remote loopback mode:
s s
Transmitted data is retimed with a maximum delay of 2 bits. Received data is retransmitted on the TFDL.
The transmitter should be disabled. The receiver can be disabled or, if desired, enabled. Received data is sent as usual to the receive FIFO if the receiver is enabled
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Facility Data Link (continued)
XMIT HDLC FDL BLOCK TFDL XMIT FIFO XMIT HDLC FDL XMIT INTERFACE TFDLCK
RFDLCK RCVR FIFO RCVR HDLC FDL RCVR INTERFACE RFDL RCVR HDLC FDL BLOCK
5-4563(F)r.1
Figure 35. Remote Loopback Mode
Phase-Lock Loop Circuit
The TFRA08C13 allows for independent transmit path and receive path clocking. The device provides outputs to control variable clock oscillators on both the transmit and receive paths. As such, the system may have both the transmit and receive paths phase-locked to two autonomous clock sources. The block diagram of the TFRA08C13 phase detector circuitry is shown in Figure 36. The TFRA08C13 uses elastic store buffers (two frames) to accommodate the transfer of data from the system interface clock rate of 2.048 Mbits/s to the line interface clock rate of either 1.544 Mbits/s or 2.048 Mbits/s. The transmit line side of the TFRA08C13 does not have any mechanism to monitor data overruns or underruns (slips) in its elastic store buffer. This interface relies on the requirement that the PLLCK clock signal (variable) is phase-locked to the CHICK clock signal (reference). When this requirement is not met, uncontrolled slips may occur in the transmit elastic store buffer that would result in corrupting data and no indication will be given. Typically, a variable clock oscillator (VCXO) is used to drive the PLLCK signal. The TFRA08C13 provides a phase error signal (PLLCK-EPLL) that can be used to control the VCXO PLLCK. The PLLCK-EPLL signal is generated by monitoring the divided-down PLLCK (DIV-PLLCK) and CHICK (DIV-CHICK) signals. The DIV-CHICK signal is used as the reference to determine the phase difference between DIV-CHICK and DIV-PLLCK. While 96
DIV-CHICK and DIVPLLCK are phase-locked, the PLLCK-EPLL signal is in a high-impedance state. A phase difference between DIV-CHICK and DIV-PLLCK drives PLLCK-EPLL to either 3.3 V or 0 V. An appropriate loop filter, for example, an RC circuit with R = 1 k and C = 0.1 F, is used to filter these PLLCK-EPLL pulses to control the VCXO. The system can force CHICK to be phase-locked to RLCK by using RLCK as a reference signal to control a VCXO that is sourcing the CHICK signal. The TFRA08C13 uses the receive line signal (RLCK) as the reference and the CHICK signal as the variable signal. The TFRA08C13 provides a phase error signal (CHICK-EPLL) that can be used to control the VCXO generating CHICK. The CHICK-EPLL signal is generated by monitoring the divided-down CHICK signal (DIV-CHICK) and RLCK (DIV-RLCK) signals. The DIVRLCK signal is used as the reference to determine the phase difference between DIV-CHICK and DIV-RLCK. While DIV-RLCK and DIV-CHICK are phase-locked, the CHICK-EPLL signal is in a high-impedance state. A phase difference between DIV-RLCK and DIV-CHICK drives CHICK-EPLL to either 3.3 V or 0 V. An appropriate loop filter, for example, an RC circuit with R = 1 k and C = 0.1 F, is used to filter these CHICK-EPLL pulses to control the VCXO. In this mode, the TFRA08C13 can be programmed to act as a master timing source and is capable of generating the system frame synchronization signal through the CHIFS pin and setting FRM_PR45 bit 4 to 1. Lucent Technologies Inc. Lucent Technologies Inc.
Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Phase-Lock Loop Circuit (continued)
EXTERNAL CIRCUIT VOLTAGECONTROLLED CRYSTAL OSCILLATOR (VCXO)
PLLCK
DIV-PLLCK
PLLCK-EPLL
DIV-CHICK
PLLCK DIVIDER CIRCUIT INTERNAL_XLCK
DIGITAL PHASE DETECTOR
CHICK DIVIDER CIRCUIT
INTERNAL_CHICK CHICK TLCK TRANSMIT FRAMER TPD, TND
FACILITY DATA READ ADDRESS
TRANSMIT 2-FRAME ELASTIC STORE BUFFER
WRITE ADDRESS
SYSTEM DATA
RECEIVE CONCENTRATION HIGHWAY INTERFACE
CHIFS RCHIDATA
BUFFER OVERRUN BUFFER UNDERRUN
SLIP MONITOR
RPD, RND RLCK RECEIVE FRAMER
WRITE ADDRESS
FACILITY DATA
RECEIVE 2-FRAME ELASTIC STORE BUFFER
READ ADDRESS
SYSTEM DATA
TRANSMIT CONCENTRATION HIGHWAY INTERFACE
TCHIDATA CHIFS CHICK
INTERNAL_RLCK RLCK DIVIDER CIRCUIT DIV-RLCK DIGITAL PHASE DETECTOR CHICK_EPLL
INTERNAL_CHICK CHICK DIVIDER CIRCUIT DIV-CHICK
VOLTAGECONTROLLED CRYSTAL OSCILLATOR (VCXO) EXTERNAL CIRCUIT
5-5268(F).a
Figure 36. TFRA08C13 Phase Detector Circuitry
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Framer-System Interface
DS1 Modes
The DS1 framing formats require rate adaptation from the 1.544 Mbits/s line interface bit stream to the system interface which functions at multiples of a 2.048 Mbits/s bit stream. The rate adaptation results in the need for eight stuffed time slots on the system interface since there are only 24 DS1 (1.544 Mbits/s) payload time slots while there are 32 system (2.048 Mbits/s) time slots. Placement of the stuffed time slots is defined by register FRM_PR43 bit 0--bit 2.
Concentration Highway Interface
Each framer has a dual, high-speed, serial interface to the system known as the CHI. This flexible bus architecture allows the user to directly interface to other Lucent components which use this interface, as well as to Mitel* and AMD TDM highway interfaces, with no glue logic. Configured via the highway control registers FRM_PR45 through FRM_PR66, this interface can be set up in a number of different configurations. The following is a list of the CHI features:
s
Lucent Technologies standard interface for communication devices. Two pairs of transmit and receive paths to carry data in 8-bit time slots. Programmable definition of highways through offset and clock-edge options which are independent for transmit and receive directions. Programmable idle code substitution of received time slots. Programmable 3-state control of each transmit time slot. Independent transmit and receive framing signals to synchronize each direction of data flow. An 8 kHz frame synchronization signal internally generated from the received line clock. Compatible with Mitel and AMD PCM highways.
CEPT Modes
The framer maps the line time slots into the corresponding system time slot one-to-one. Framing time slot 0, the FAS and NFAS bytes, are placed in system time slot 0.
s
s
s
Receive Elastic Store
The receive interface between the framer and the system CHI includes a 2-frame elastic store buffer to enable rate adaptation. The receive line elastic store buffer contains circuitry that monitors the read and write pointers for potential data overrun and underrun (slips) conditions. Whenever this slip circuitry determines that a slip may occur in the receive elastic store buffer, it will adjust the read pointer such that a controlled slip is performed. The controlled slip is implemented by dropping or repeating a complete frame at the frame boundaries. The occurrence of controlled slips in the receive elastic store are indicated in the status register FRM_SR3 bit 6 and bit 7.
s
s
s
s
Supported is the optional configuration of the CHI which presents the signaling information along with the data in any framing modes when the device is programmed for the associated signaling mode (ASM). This mode is discussed in the signaling section. Data can be transmitted or received on either one of two interface ports, called CHIDATA and CHIDATAB. The user-supplied clock (CHICLK) controls the timing on the transmit or receive paths. Individual time slots are referenced to the frame synchronization (CHIFS) pulse. Each frame consists of 32 time slots at a programmable data rate of 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s requiring a clock (CHICK) of the same rate. The clock and data rates of the transmit and receive highways are programmed independently.
Transmit Elastic Store
The transmit interface between the framer and the system CHI includes a 2-frame elastic store buffer to enable rate adaptation. The line transmit clock applied to PLLCK[1--8] must be phase-locked to CHICK. No indication of a slip in the transmit elastic store is given.
* Mitel is a registered trademark of Mitel Corporation. AMD is a registered trademark of Advanced Micro Devices, Inc.
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TFRA08C13 OCTAL T1/E1 Framer
the first, second, third, or fourth time slot) or be grouped together at the end of the CHI frame as described in register FRM_PR43 bit 0--bit 2. The positioning of the idle time slots is the same for transmit and receive directions. Idle time slots contain the programmable code of register FRM_PR23. Unused time slots can be disabled by forcing the TCHIDATA interface to a high-impedance state for the interval of the disabled time slots.
Concentration Highway Interface
(continued) Rate adaptation is required for all DS1 formats between the 1.544 Mbits/s line rate and 2.048 Mbits/s, 4.966 Mbits/s, or 8.182 Mbits/s CHI rate. This is achieved by means of stuffing eight idle time slots into the existing twenty-four time slots of the T1 frame. Idle time slots can occur every fourth time slot (starting in
CHI Parameters
The CHI parameters that define the receive and transmit paths are given in Table 45. Table 45. Summary of the TFRA08C13's Concentration Highway Interface Parameters Name HWYEN Description Highway Enable (FRM_PR45 bit 7). A 1 in this bit enables the transmit and receive concentration highway interfaces. This allows the framer to be fully configured before transmission to the highway. A 0 forces the idle code as defined in register FRM_PR22, to be transmitted to the line in all payload time slots while TCHIDATA is forced to a high-impedance state for all CHI transmitted time slots. Concentration Highway Master Mode (PRM_PR45 bit 4). The default mode CHIMM = 0 enables an external system frame synchronization signal (CHIFS) to drive the transmit CHI. A 1 enables the transmit CHI to generate a system frame synchronization signal from the receive line clock. The transmit CHI system frame synchronization signal is generated on the CHIFS output pin. Applications using the receive line clock as the reference clock signal of the system are recommended to enable this mode and use the CHIFS signal generated by the framer. The receive CHI path is not affected by this mode. CHI Double Time-Slot Mode (FRM_PR65 bit 1 and FRM_PR66 bit 1). CHIDTS defines the 4.096 Mbits/s and 8.192 Mbits/s CHI modes. CHIDTS = 0 enables the 32 contiguous time-slot mode. This is the default mode. CHIDTS = 1 enables the double time-slot mode in which the transmit CHI drives TCHIDATA for one time slot and then 3-states for the subsequent time slot, and the receive CHI latches data from RCHIDATA for one time slot and then ignores the following time slot and so on. CHIDTS = 1 allows two CHIs to interleave frames on a common bus. Transmit Frame Edge (FRM_PR46 bit 3). TFE = 0 (or 1), CHIFS is sampled on the falling (or rising) edge of CHICK. In CHIMM (CHI master mode), the CHIFS pin outputs a transmit frame strobe to provide synchronization for TCHIDATA. When TFE = 1 (or 0), CHIFS is centered around rising (or falling) edge of CHICK. In this mode, CHIFS can be used for receive data on RCHIDATA. The timing for CHIFS in CHIMM = 1 mode is identical to the timing for CHIFS in CHIMM = 0 mode. Receive Frame Edge (FRM_PR46 bit 7). RFE = 0 (or 1), CHIFS is sampled on the falling (or rising) edge of CHICK. CHI Data Rate (FRM_PR45 bit 2 and bit 3). Two-bit control for selecting the CHI data rate. The default state (00) enables the 2.048 Mbits/s. CDRS Bit: 23 CHI Data Rate 00 2.048 Mbits/s 01 4.096 Mbits/s 10 8.192 Mbits/s 11 Reserved 99
CHIMM
CHIDTS
TFE
RFE CDRS0--CDRS1
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TFRA08C13 OCTAL T1/E1 Framer
Preliminary Data Sheet October 2000
Concentration Highway Interface (continued)
Table 45. Summary of the TFRA08C13's Concentration Highway Interface Parameters (continued) Name TCE RCE TTSE31--TTSE0 Description Transmitter Clock Edge (FRM_PR47 bit 6). TCE = 0 (or 1), TCHIDATA is clocked on the falling (or rising) edge of CHICK. Receiver Clock Edge (FRM_PR48 bit 6). RCE = 0 (or 1), RCHIDATA is latched on the falling (or rising) edge of CHICK. Transmit Time-Slot Enable 31--0 (FRM_PR49--FRM_PR52). These bits define which transmit CHI time slots are enabled. A 1 enables the TCHIDATA or TCHIDATAB time slot. A 0 forces the CHI transmit highway time slot to be 3-stated. Receive Time-Slot Enable 31--0 (FRM_PR53--FRM_PR56). These bits define which receive CHI time slots are enabled. A 1 enables the RCHIDATA or RCHDATAB time slots. A 0 disables the time slot and transmits the programmable idle code of register FRM_PR22 to the line interface. Transmit Highway Select 31--0 (FRM_PR57--FRM_PR60). These bits define which transmit CHI highway, TCHIDATA or TCHIDATAB, contains valid data for the active time slot. A 0 enables TCHIDATA; a 1 enables the TCHIDATAB. Receive Highway Select 31--0 (FRM_PR61--FRM_PR64). These bits define which receive CHI highway, RCHIDATA or RCHIDATAB, contains valid data for the active time slot. A 0 enables RCHIDATA; a 1 enables the RCHIDATAB. Transmitter Bit Offset (FRM_PR46 bit 0--bit 2). These bits are used in conjunction with the transmitter byte offset to define the beginning of the transmit frame. They determine the offset relative to TCHIFS, for the first bit of transmit time slot 0. The offset is the number of CHICK cycles by which the first bit is delayed. Receiver Bit Offset (FRM_PR46 bit 4--bit 6). These bits are used in conjunction with the receiver byte offset to define the beginning of the receiver frame. They determine the offset relative to the RCHIFS, for the first bit of receive time slot 0. The offset is the number of CHICK cycles by which the first bit is delayed. Transmitter Byte Offset (FRM_PR47 bit 0--bit 5 and FRM_PR65 bit 0). These bits determine the offset from the CHIFS to the beginning of the next frame on the transmit highway. Note that in the ASM mode, a frame consists of 64 contiguous bytes; whereas in other modes, a frame contains 32 contiguous bytes. Allowable offsets: 2.048 Mbits/s 0--31 bytes. 4.096 Mbits/s 0--63 bytes. 8.192 Mbits/s 0--127 bytes. Receiver Byte Offset (FRM_PR48 bit 0--bit 5 and FRM_PR66 bit 0). These bits determine the offset from CHIFS to the beginning of the receive CHI frame. Note that in the ASM mode, a frame consists of 64 contiguous bytes; whereas in other modes, a frame contains 32 contiguous bytes. Allowable offsets: 2.048 Mbits/s 0--31 bytes. 4.096 Mbits/s 0--63 bytes. 8.192 Mbits/s 0--127 bytes. Associated Signaling Mode (FRM_PR44 bit 2). When enabled, the associate signaling mode configures the CHI to carry both payload data and its associated signaling information. Enabling this mode must be in conjunction with the programming of the CHI data rate to either 4.048 Mbits/s or 8.096 Mbits/s. Each time slot consists of 16 bits where 8 bits are data and the remaining 8 bits are signaling information. Stuffed Time Slots (FRM_PR43 bit 0--bit 2). Valid only in T1 framing formats, these 3 bits define the location of the eight stuffed CHI (unused) time slots.
RTSE31--RTSE0
THS31--THS0
RHS31--RHS0
TOFF2--TOFF0
ROFF2--ROFF0
TBYOFF6--TBYOFF0
RBYOFF6--RBYOFF0
ASM
STS0--STS2
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TFRA08C13 OCTAL T1/E1 Framer
Concentration Highway Interface (continued)
CHI Frame Timing
CHI Timing with CHIDTS Disabled Figure 37 illustrates the CHI frame timing when CHIDTS is disabled (registers FRM_PR65 bit 1 (TCHIDTS) and FRM_PR66 bit 1 (RCHDTS) = 0) and the CHI is not in the associated signaling mode (FRM_PR44 bit 2 (ASM) = 0). The frames are 125 ms long and consist of 32 contiguous time slots. In DS1 frame modes, the CHI frame consists of 24 payload time slots and eight stuffed (unused) time slots. In CEPT frame modes, the CHI frame consists of 32 payload time slots.
125 s
CHIFS DS1 FORMAT 2.048 Mbits/s CHI: TCHIDATA
FRAME 1 24 VALID TIME SLOTS HIGH IMPEDANCE 8 STUFFED SLOTS* FRAME 2
RCHIDATA CEPT FORMAT 2.048 Mbits/s CHI:
24 VALID TIME SLOTS
FRAME 2
32 VALID TIME SLOTS TCHIDATA or RCHIDATA FRAME 1 FRAME 2
4.096 Mbits/s CHI: HIGH IMPEDANCE
TCHIDATA
FRAME 1
FRAME 2
RCHIDATA
FRAME 1
FRAME 2
8.192 Mbits/s CHI: TCHIDATA FRAME 1 HIGH IMPEDANCE FRAME 2
RCHIDATA
FRAME 1
FRAME 2
5-5269(F).ar.2
* The position of the stuffed time is controlled by register FRM_PR43 bit 0--bit 2.
Figure 37. Nominal Concentration Highway Interface Timing (for FRM_PR43 bit 0--bit 2 = 100 (Binary))
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Concentration Highway Interface (continued)
CHI Timing with CHIDTS Enabled Figure 38 illustrates the CHI frame timing when CHIDTS is enabled (registers FRM_PR65 bit 1 (TCHIDTS) and FRM_PR66 bit 1 (RCHIDTS) = 1) and ASM is disabled (register FRM_PR44 bit 2 (ASM) = 0). In the CHIDTS mode, valid CHI payload time slots are alternated with high-impedance intervals of one time-slot duration. This mode is valid only for 4.096 Mbits/s and 8.192 Mbits/s CHI rates.
125 s
CHIFS
4.096 Mbits/s CHI
TIME TIME SLOT SLOT
FRAME 1
FRAME 2
TCHIDATA
TS0 8 bits
TS1
TS2
TS3
TS4
TS30
TS31
TS0
RCHIDATA
TS0
TS1
TS2
TS3
TS4
T30
TS31
TS0
8.192 Mbits/s CHI TCHIDATA
TS0 TS1 TS2 TS30 TS31
HIGH IMPEDANCE
TS0
RCHIDATA
TS0
TS1
TS2
TS30
TS31
TS0
5-6454(F)r.3
Figure 38. CHIDTS Mode Concentration Highway Interface Timing
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TFRA08C13 OCTAL T1/E1 Framer
Concentration Highway Interface (continued)
CHI Timing with Associated Signaling Mode Enabled Figure 39 illustrates the CHI frame timing when the associated signaling mode is enabled (register FRM_PR44 bit 2 (ASM) = 1) and the CHIDTS mode is disabled (registers FRM_PR65 bit 1 (TCHIDTS) = 0 and FRM_PR66 bit 1 (RCHIDTS) = 0). The frames are 125 ms long and consist of 32 contiguous 16-bit time slots. In DS1 frame formats, each frame consists of 24 time slots and eight stuffed time slots. Each time slot consists of two octets. In CEPT modes, each frame consists of 32 time slots. Each time slot consists of two octets.
125 s
CHIFS 4.096 Mbits/s CHI: TCHIDATA or RCHIDATA FRAME = 64 bytes: 32 DATA + 32 SIGNALING FRAME 1 FRAME 2
DATA AND SIGNALING BYTES ARE INTERLEAVED DATA 0 SIGNALING 0 DATA 31 SIGNALING 31 DATA 0
FRAME 8.192 Mbits/s CHI: TCHIDATA FRAME 1 HIGH IMPEDANCE FRAME 2
RCHIDATA
FRAME 1
FRAME 2
5-5270(F).ar.3
Figure 39. Associated Signaling Mode Concentration Highway Interface Timing CHI Timing with Associated Signaling Mode and CHIDTS Enabled Figure 40 illustrates the CHI frame timing in the associated signaling mode (register FRM_PR44 bit 2 (ASM) = 1) and CHIDTS enabled (registers FRM_PR65 bit 1 (TCHIDTS) = 1 and FRM_PR66 bit 1 (RCHIDTS) = 1).
8.192 Mbits/s CHI WITH ASM (ASSOCIATED SIGNALING MODE) ENABLED
TS0 TCHIDATA OR RCHIDATA TS1 TS31 TS0
*
DATA
SIGNALING
*
*
DATA
SIGNALING
16 bits 1 TIME SLOT
16 bits 1 TIME SLOT
5-6454(F).ar.2
* High-impedance state for TCHIDATA and not received (don't care) for RCHIDATA.
Figure 40. CHI Timing with ASM and CHIDTS Enabled Lucent Technologies Inc. Lucent Technologies Inc. 103
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Concentration Highway Interface (continued)
CHI Offset Programming
To facilitate bit offset programming, two additional internal parameters are introduced: CEX is defined as the clock edge with which the first bit of time slot 0 is transmitted; CER is defined as the clock edge on which bit 0 of time slot 0 is latched. CEX and CER are counted relative to the edge on which the CHIFS signal is sampled. Values of CEX and CER depend upon the values of the parameters described above. The following table gives decimal values of CEX and CER for various values of TFE, RFE, TCE, RCE, TOFF[2:0], and ROFF[2:0]. The byte (time slot) offsets are assumed to be zero in the following examples. Table 46. Programming Values for TOFF[2:0] and ROFF[2:0] when CMS = 0 RFE/ TFE 0 0 1 1 RCE/ TCE 0 1 0 1 ROFF[2:0] or TOFF[2:0] 000 4 3 3 4 001 6 5 5 6 010 8 7 7 8 011 10 9 9 10 100 12 11 11 12 101 14 13 13 14 110 16 15 15 16 111 18 17 17 18 CER or CEX (decimal)
Figure 41 shows an example of the relative timing of CHI 2.048 Mbits/s data with the following parameters:
s s s
CMS = 0, TFE, RFE = 0. TCE = 1, TOFF[2:0] = 000, TBYOFF[6:0] = 0000000. RCE = 0, ROFF[2:0] = 000, RBYOFF[6:0] = 0000000.
CHIFS IS SAMPLED ON THIS EDGE: FE = 0 1 2 3 4 5 6 7 8
CHICK
CHIFS
CEX = 3 TCHIDATA: TCE = 1 HIGH IMPEDANCE BIT 0, TS 0 CER = 4 RCHIDATA: RCE = 0 BIT 0, TS 0 BIT 1, TS 0 BIT 2, TS 0
5-2202(F).d
BIT 1, TS 0
BIT 2, TS 0
Figure 41. TCHIDATA and RCHIDATA to CHICK Relationship with CMS = 0 * The ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release is controlled by one set of bit stream options, and the = 3 and CER = 4, Respectively) (CEX timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options.
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TFRA08C13 OCTAL T1/E1 Framer
Concentration Highway Interface (continued)
Figure 42 and Figure 43 illustrate the CHI timing.
CHICLK t14S t14H t14S: CHIFS SETUP = 30 ns min t14H: CHIFS HOLD = 45 ns min CHIFS
t15S RCHIDATA
t15H t15S: RCHIDATA SETUP = 25 ns min t15S: RCHIDATA HOLD = 25 ns min
5-3916(F).d
Note: For case illustrated, RFE = 0, and RCE = 0.
Figure 42. Receive CHI (RCHIDATA) Timing
CHICLK t14S t14H t14S: CHIFS SETUP = 35 ns min t14H: CHIFS HOLD = 45 ns min CHIFS
t19 TCHIDATA
t19: CHICK TO TCHIDATA DELAY = 25 ns max
5-3917(F).d
Note: For case illustrated, TFE = 0 and TCE = 0.
Figure 43. Transmit CHI (TCHIDATA) Timing
JTAG Boundary-Scan Specification
Principle of the Boundary Scan
The boundary scan (BS) is a test aid for chip, module, and system testing. The key aspects of BS are as follows:
s
Testing the connections between ICs on a particular board. Observation of signals to the IC pins during normal operating functions. Controlling the built-in-self-test (BIST) of an IC. TFRA08C13 does not support BS-BIST.
s
s
Designed according to the IEEE Std. 1149.1-1990 standard, the BS test logic consists of a defined interface: the test access port (TAP). The TAP is made up of four signal pins assigned solely for test purposes. The fifth test pin ensures that the test logic is initialized asynchronously. The BS test logic also comprises a 16state TAP controller, an instruction register with a decoder, and several test data registers (BS register, BYPASS register, and IDCODE register). The main component is the BS register that links all the chip pins to a shift register by means of special logic cells. The test logic is designed in such a way that it is operated independently of the application logic of the TFRA08C13 (the mode multiplexer of the BS output cells may be shared). Figure 44 illustrates the block diagram of the TFRA08C13's BS test logic.
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JTAG Boundary-Scan Specification (continued)
BOUNDARY-SCAN REGISTER
CHIP KERNEL IN OUT
(UNAFFECTED BY BOUNDARY-SCAN TEST)
IDCODE REGISTER
BYPASS REGISTER TDI INSTRUCTION REGISTER TRST
MUX
TDO
TMS TCK TAP CONTROLLER
INSTRUCTION DECODER
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Figure 44. Block Diagram of the TFRA08C13's Boundary-Scan Test Logic
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JTAG Boundary-Scan Specification (continued)
Test Access Port Controller
The test access port controller is a synchronous sequence controller with 16 states. The state changes are preset by the TMS, TCK, and TRST signals and by the previous state. The state changes always take place when the TCK edge rises. Figure 45 shows the TAP controller state diagram.
TRST = 0
TEST LOGIC RESET 1 0 RUN TEST/ IDLE 0 1 1 SELECT-DR 0 CAPTURE-DR 0 SHIFT-DR 0 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 1 1 EXIT1-IR 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 0 0 1 1 SELECT-IR 0 CAPTURE-IR 0 SHIFT-IR 0 1
5-3924(F)r.5
Figure 45. BS TAP Controller State Diagram
The value shown next to each state transition in Figure 45 represents the signal present at TMS at the time of a rising edge at TCK. The description of the TAP controller states is given in IEEE Std. 1149.1-1990 Section 5.1.2 and is reproduced in Table 49 and Table 50.
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JTAG Boundary-Scan Specification (continued)
Table 47. TAP Controller States in the Data Register Branch Name TEST LOGIC RESET Description The BS logic is switched in such a way that normal operation of the ASIC is adjusted. The IDCODE instruction is initialized by TEST LOGIC RESET. Irrespective of the initial state, the TAP controller has achieved TEST LOGIC RESET after five control pulses at the latest when TMS = 1. The TAP controller then remains in this state. This state is also achieved when TRST = 0. Using the appropriate instructions, this state can activate circuit parts or initiate a test. All of the registers remain in their present state if other instructions are used. This state is used for branching to the test data register control. The test data is loaded in the test data register parallel to the rising edge of TCK in this state. The test data is clocked by the test data register serially to the rising edge of TCK in the state. The TDO output driver is active. This temporary state causes a branch to a subsequent state. The input and output of test data can be interrupted in this state. The test data is clocked into the second stage of the test data register parallel to the falling edge of TCK in this state.
RUN TEST/IDLE
SELECT-DR CAPTURE-DR SHIFT-DR EXIT(1/2)-DR PAUSE-DR UPDATE-DR
Table 48. TAP Controller States in the Instruction Register Branch Name SELECT-IR CAPTURE-IR SHIFT-IR EXIT(1/2)-IR PAUSE-IR UPDATE-IR Description This state is used for branching to the instruction register control. The instruction code 0001 is loaded in the first stage of the instruction register parallel to the rising edge of TCK in this state. The instructions are clocked into the instruction register serially to the rising edge of TCK in the state. The TDO output driver is active. This temporary state causes a branch to a subsequent state. The input and output of instructions can be interrupted in this state. The instruction is clocked into the second stage of the instruction register parallel to the falling edge of TCK in this state.
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Instruction Register
The instruction register (IR) is 4 bits in length. Table 49 shows the BS instructions implemented by the TFRA08C13. Table 49. TFRA08C13's Boundary-Scan Instructions Instruction EXTEST IDCODE HIGHZ SAMPLE/PRELOAD BYPASS EVERYTHING ELSE Code 0000 0001 0100 0101 1111 -- Act. Register TDITDO Boundary Scan Identification BYPASS Boundary Scan BYPASS BYPASS Mode TEST NORMAL X NORMAL NORMAL X Function Test external connections Read Manuf. Register 3-state Sample/load Min. shift path -- Output Defined Via BS Register Core Logic Output--High Impedance Core Logic Core Logic Output--High Impedance
The instructions not supported in TFRA08C13 are INTEST, RUNBIST, TOGGLE. A fixed binary 0001 pattern (the 1 into the least significant bit) is loaded into the IR in the capture-IR controller state. The IDCODE instruction (binary 0001) is loaded into the IR during the test-logic-reset controller state and at powerup. The following is an explanation of the instructions supported by TFRA08C13 and their effect on the devices' pins. EXTEST This instruction enables the path cells, the pins of the ICs, and the connections between ASICs to be tested via the circuit board. The test data can be loaded in the chosen position of the BS register by means of the SAMPLE/PRELOAD instruction. The EXTEST instruction selects the BS register as the test data register. The data at the function inputs is clocked into the BS register on the rising edge of TCK in the CAPTURE-DR state. The contents of the BS register can be clocked out via TDO in the SHIFT-DR state. The value of the function outputs is solely determined by the contents of the data clocked into the BS register and only changes in the UPDATE-DR state on the falling edge of TCK.
DCODE Information regarding the manufacturer's ID for Lucent, the IC number, and the version number can be read out serially by means of the IDCODE instruction. The IDCODE register is selected, and the BS register is set to normal mode in the UPDATE-IR state. The IDCODE is loaded at the rising edge of TCK in the CAPTUREDR state. The IDCODE register is read out via TDO in the SHIFT-DR state. HIGHZ All 3-statable outputs are forced to a high-impedance state, and all bidirectional ports to an input state by means of the HIGHZ instruction. The impedance of the outputs is set to high in the UPDATE-IR state. The function outputs are only determined in accordance with another instruction if a different instruction becomes active in the UPDATE-IR state. The BYPASS register is selected as the test data register. The HIGHZ instruction is implemented in a similar manner to that used for the BYPASS instruction. SAMPLE/PRELOAD The SAMPLE/PRELOAD instruction enables all the input and output pins to be sampled during operation (SAMPLE) and the result to be output via the shift chain. This instruction does not impair the internal logic functions. Defined values can be serially loaded in the BS cells via TDI while the data is being output (PRELOAD).
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BYPASS This instruction selects the BYPASS register. A minimal shift path exists between TDI and TDO. The BYPASS register is selected after the UPDATE-IR. The BS register is in normal mode. A 0 is clocked into the BYPASS register during CAPTURE-DR state. Data can be shifted by the BYPASS register during SHIFT-DR. The contents of the BS register do not change in the UPDATE-DR state. Please note that a 0 that was loaded during CAPTURE-DR appears first when the data is being read out.
Boundary-Scan Register
The boundary-scan register is a shift register, whereby one or more BS cells are assigned to every digital TFRA08C13 pin (with the exception of the pins for the BS architecture, analog signals, and supply voltages). The TFRA08C13's boundary-scan register bit-to-pin assignment is defined in the BSDL file, which is available upon request. Please call 1-800-TECKFAX (1-800-832-5329).
BYPASS Register
The BYPASS register is a one-stage shift register that enables the shift chain to be reduced to one stage in the TFRA08C13.
DCODE Register
The IDCODE register identifies the TFRA08C13 by means of a parallel, loadable, 32-bit shift register. The code is loaded on the rising edge of TCK in the CAPTURE-DR state. The 32-bit data is organized into four sections as follows. Table 50. IDCODE Register Version Bits 31--28 0001 Part Number Bits 27--12 0111011000110100 Manufacturer ID Bits 11--1 00000011101 1 Bit 0 1
3-State Procedures
The 3-state input participates in the boundary scan. It has a BS cell, but buffer blocking via this input is suppressed for the EXTEST instruction. The 3-state input is regarded as a signal input that is to participate in the connection test during EXTEST. The buffer blocking function should not be active during EXTEST to ensure that the update pattern at the TFRA08C13 outputs does not become corrupted.
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global interrupt register) and reads the specific alarm status registers, the INTERRUPT output will deassert. In the polled mode, however, the microprocessor monitors the various device alarm status by periodically reading the alarm status registers within the TFRA08C13 without the use of INTERRUPT. In both interrupt and polled methods of alarm servicing, the status registers within an identified block will clear on a microprocessor read cycle only when the alarm condition within that block no longer exists; otherwise, the alarm status register bit remains set. The powerup default states for the line interface unit, framer, and the HDLC blocks are discussed in their respective sections. All read/write registers within these blocks must be written by the microprocessor on system start-up to guarantee proper device functionality. Register addresses not defined in this data sheet must not be written. Details concerning the microprocessor interface configuration modes, pinout definitions, clock specifications, register address map, I/O timing specifications, and the I/O timing diagrams are described in the following sections.
Microprocessor Interface
Overview
The TFRA08C13 device is equipped with a microprocessor interface that can operate with most commercially available microprocessors. The microprocessor interface provides access to all the internal registers through a 12-bit address bus and an 8-bit data bus. Input MPMODE (pin AF9) is used to configure this interface into one of two possible modes, as shown in Table 51. The MPMODE setting selects the associated set of control signals required to access a set of registers within the device. The microprocessor interface can operate at speeds up to 33 MHz in interrupt-driven or polled mode without requiring any wait-states. For microprocessors operating at greater than 33 MHz, the RDY_DTACK output (pin V26) may be used to introduce wait-states in the read/write cycles. In the interrupt-driven mode, one or more device alarms will assert the INTERRUPT output (pin AD9) once per alarm activation. After the microprocessor identifies the source(s) of the alarm(s) (by reading the
Microprocessor Configuration Modes
Table 51 highlights the two microprocessor modes controlled by the MPMODE input (pin AF9) Table 51. Microprocessor Configuration Modes Mode Mode 1 Mode 3 MPMODE 0 1 Generic Control, Data, and Output Pin Names
CS, AS, DS, R/W, A[11:0], D[7:0], INTERRUPT, DTACK* CS, ALE, RD, WR, A[11:0], D[7:0], INTERRUPT, RDY
* The DTACK signal is asynchronous to the MPCLK signal.
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Microprocessor Interface (continued)
Microprocessor Interface Pinout Definitions
The Mode [1 and 3] specific pin definitions are given in Table 52. Note that the microprocessor interface uses the same set of pins in all modes. Table 52. Mode [1 and 3] Microprocessor Pin Definitions
Configuration Mode 1 Pin Number V24 U26 Device Pin Name WR_DS RD_R/W Generic Pin Name DS R/W Pin_Type Input Input Assertion Sense Active-Low -- Function Data Strobe Read/Write R/W = 1 => Read R/W = 0 => Write Address Strobe Chip Select Interrupt Data Acknowledge Data Bus Address Bus Microprocessor Clock Write Read Address Latch Enable Chip Select Interrupt Ready Data Bus Address Bus Microprocessor Clock
U23 U25 AD9 V26 Note 4 Note 4 AE10 Mode 3 V24 U26 U23 U25 AD9 V26 Note 4 Note 4 AE10
ALE_AS CS INTERRUPT RDY_DTACK D[7:0] A[11:0] MPCLK WR_DS RD_R/W ALE_AS CS INTERRUPT RDY_DTACK D[7:0] A[11:0] MPCLK
AS CS INTERRUPT1 DTACK3 D[7:0] A[11:0] MPCLK WR RD ALE CS INTERRUPT RDY5 D[7:0] A[11:0] MPCLK
1
Input Input Output Output I/O Input Input Input Input Input Input Output Output I/O Input Input
Active-Low Active-Low Active-High/ Low2 Active-Low -- -- -- Active-Low Active-Low Active-Low Active-Low Active-High/ Low Active-High -- -- --
1. INTERRUPT output is synchronous to the internal clock source RLCK-LIU. If RLCK_LIU is absent, the reference clock for interrupt timing becomes an interval 2.048 MHz clock derived from the CHI clock. 2. In the default (reset) mode, INTERRUPT is active-high. It can be made active-low by setting register GREG4 bit 6 to 1. 3. The DTACK output is asynchronous to MPCLK. 4. See Table 2. Pin Descriptions. 5. MPCLK is needed if RDY output is required to be synchronous to MPCLK.
Microprocessor Clock (MPCLK) Specifications
The microprocessor interface is designed to operate at clock speeds up to 16 MHz without requiring any waitstates. Wait-states may be needed if higher microprocessor clock speeds are required. The microprocessor clock (MPCLK, pin AE10) specification is shown in Table 53. This clock must be supplied only if the RDY (MODE 3) is required to be synchronous to MPCLK. Table 53. Microprocessor Input Clock Specifications Name MPCLK 112 Symbol t1 Period and Tolerance 30 to 323 Trise Typ 2 Tfall Typ 2 Duty Cycle Min High 12 Min Low 12 ns Lucent Technologies Inc. Lucent Technologies Inc. Unit
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Microprocessor Interface (continued)
Microprocessor Interface Register Address Map
The register address space is divided into thirteen (13) contiguous banks of 512 addressable units each. Each addressable unit is an 8-bit register. These register banks are labeled as REGBANK[0--12]. The register address map table gives the address range of these register banks and their associated circuit blocks. REGBANK0 contains the global registers which are common to all the circuit blocks on the TFRA08C13. REGBANK[1--8] are attached to the framer circuit blocks. REGBANK[9--12] are attached to the FDL circuit blocks. The descriptions of the individual register banks can be found in the appropriate sections of this document. In these descriptions, all addresses are given in hexadecimal. Addresses out of the range specified by Table 54 must not be addressed. If they are written, they must be written to 0. An inadvertent write to an out-of-range address may be corrected by a device reset. Table 54. TFRA08C13 Register Address Map Register Bank Label Start Address End Address (in Hex) (in Hex) REGBANK0 REGBANK1 REGBANK2 REGBANK3 REGBANK4 REGBANK5 REGBANK6 REGBANK7 REGBANK8 REGBANK9 REGBANK10 REGBANK11 REGBANK12 000 200 2E0 300 3E0 400 4E0 500 5E0 600 6E0 700 7E0 800 8E0 900 9E0 A00 A20 B00 B20 C00 C20 D00 D20 008 2A6 2FF 3A6 3FF 4A6 4FF 5A6 5FF 6A6 6FF 7A6 7FF 8A6 8FF 9A6 9FF A0E A2F B0E B2F C0E C2F D0E D2F Circuit Block Name Octal Global Registers* Framer1 Framer2 Framer3 Framer4 Framer5 Framer6 Framer7 Framer8 Facility Data Link 1 (FDL1) Facility Data Link 2 (FDL2) Facility Data Link 3 (FDL3) Facility Data Link 4 (FDL4) Facility Data Link 5 (FDL5) Facility Data Link 6 (FDL6) Facility Data Link 7 (FDL7) Facility Data Link 8 (FDL8)
* Core registers are common to all circuit blocks on the TFRA08C13.
I/O Timing*
The I/O timing specifications for the microprocessor interface are given in Table 55. The microprocessor interface pins are compatible with CMOS/TTL I/O levels. All outputs, except the data bus D[7:0], are rated for a capacitive load of 50 pF. The D[7:0] outputs are rated for a 100 pF load.
* See Product Advisory AY99-041 for more information.
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Table 55. Microprocessor Interface I/O Timing Specifications Symbol Configuration Parameter Setup (ns) (Min) -- 10 -- -- 40 5 -- -- -- -- -- -- -- -- -- 10 10 -- -- -- -- -- -- -- 10 Hold (ns) (Min) 10 -- 10 -- -- -- -- -- -- -- 8 5 -- -- 5 -- -- 8 10 10 -- -- -- -- -- Delay (ns) (Max) -- -- -- -- -- -- 12 15 19 25 -- -- 12 10 -- -- -- -- -- -- -- -- -- -- --
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25
Mode 1
AS Asserted Width Address Valid to AS Deasserted AS Deasserted to Address Invalid -- R/W Valid to Both CS and DS Asserted Address Valid and AS Asserted to DS Asserted (Read) CS Asserted to DTACK Low Impedance DS Asserted to DTACK Asserted DS Asserted to AD Low Impedance (Read) DTACK Asserted to Data Valid DS Deasserted to CS Deasserted (Read) DS Deasserted to R/W Invalid DS Deasserted to DTACK Deasserted CS Deasserted to DTACK High Impedance DS Deasserted to Data Invalid (Read) Address Valid and AS asserted to DS Asserted (Write) Data Valid to DS Asserted DS Deasserted to CS Deasserted (Write) DS Deasserted to Data Valid DS Asserted Width (Write) -- -- -- -- CS Asserted to DS Asserted (Write)
Note: The read and write timing diagrams for all four microprocessor interface modes are shown in Figure 46--Figure 49.
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Table 55. Microprocessor Interface I/O Timing Specifications (continued) Symbol Configuration Parameter Setup (ns) (Min) -- 10 -- 5 5 -- -- -- -- -- -- -- -- 6 10 10 -- -- -- -- -- -- -- -- -- -- -- -- -- Hold (ns) (Min) 10 -- 10 -- -- -- -- -- -- 5 -- -- 5 -- -- -- 7 -- 10 40 50 -- -- -- -- Delay (ns) (Max) -- -- -- -- -- 12 15 19 40 -- 15 10 -- -- -- -- -- 15 -- -- -- -- -- -- --
t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42 t43 t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55
Mode 3
ALE Asserted Width Address Valid to ALE Deasserted ALE Deasserted to Address Invalid CS Asserted to RD Asserted Address Valid and ALE Asserted to RD Asserted CS Asserted to RDY Low Impedance Rising Edge MPCK to RDY Asserted RD Asserted to AD Low Impedance RD Asserted to Data Valid RD Deasserted to CS Deasserted RD Deasserted to RDY Deasserted CS Deasserted to RDY High Impedance RD Deasserted to Data Invalid (High Impedance) CS Asserted to WR Asserted Address Valid and ALE Asserted to WR Asserted Data Valid to WR Asserted WR Deasserted to CS Deasserted WR Deasserted to RDY Deasserted WR Deasserted to Data Invalid RD Asserted Width WR Asserted Width
Note: The read and write timing diagrams for all four microprocessor interface modes are shown in Figure 46--Figure 49.
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t11 CS t1 AS t2 A[0:11] VALID ADDRESS t12 R/W t5 DS t6 t7 DTACK t9 D[0:7] t10 VALID DATA
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t3
t8
t13
t14
t15
Figure 46. Mode 1--Read Cycle Timing (MPMODE = 0)
t18 CS t1 AS t2 A[0:11] VALID ADDRESS t5 R/W t16 t20 DS t25 t7 DTACK t17 D[0:7] VALID DATA
5-6423(F).a
t3
t12
t8
t13
t14
t19
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Microprocessor Interface (continued)
t40 CS t31 ALE t32 A[0:11] VALID ADDRESS t34 RD t35 t36 RDY t39 t38 D[0:7] VALID DATA t43 t37 t41 t42 t50 t33
MPCK
5-6426(F).a
Figure 48. Mode 3--Read Cycle Timing (MPMODE = 1)
t47 CS t31 ALE t32 A[0:11] VALID ADDRESS t44 WR t45 t36 RDY t46 D[0:7] VALID DATA t49 t37 t48 t42 t51 t33
MPCK
5-6427(F).a
Figure 49. Mode 3--Write Cycle Timing (MPMODE = 1) Lucent Technologies Inc. Lucent Technologies Inc. 117
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Reset
Both hardware and software resets are provided.
Hardware Reset (Pin C19)
Hardware reset is enabled by asserting RESET to 0. The device is in an inactive condition when RESET is 0, and becomes active when RESET is returned to 1. Eight cycles of the LIU receive line clock, i.e., 5.2 s for T1 or 3.9 s for E1, is required to guarantee a complete reset. Hardware reset returns all framer and FDL registers to their default values, as listed in the individual register descriptions and register maps, (Table 182--Table 186). Hardware reset results in a complete device reset including a reset of the global registers.
Software Reset/Software Restart
Independent software reset for each functional block of the device is available. The framer may be reset through register FRM_PR26 bit 0 (SWRESET), or placed in restart through FRM_PR26 bit 1 (SWRESTART). The FDL receiver may be reset through register FDL_PR26 bit 1 (FRR), and the FDL transmitter may be reset through FDL_PR1 bit 5 (FTR). The reset functions, framer SWRESET (framer software reset), FDL FRR (FDL receiver reset), and FTR (FDL transmitter reset), reset the block and return all parameter/control registers for the block to their default values. The restart function framer SWRESTART (framer software restart), resets the block but does not alter the value of the parameter/control registers.
Interrupt Generation
An interrupt may be generated by any of the conditions reported in the status registers. For a bit (condition) in a status register to create an interrupt, the corresponding interrupt enable bit must be set and the interrupt block enable in the global register for the source block must be set, see Table 56 below. Once the source interrupt register is read, the interrupt for that condition is deasserted. Table 56. Status Register and Corresponding Interrupt Enable Register for Functional Blocks Functional Block Primary Block Framer Facility Data Link Status Register GREG0 FRM_SR0--FRM_SR7 FDL_SR0 Interrupt Enable Register GREG1 FRM_PR0--FRM_PR7 FDL_PR2
Default for interrupt assertion is a logical 1 (high) value. But the assertion value and deasserted state is programmable through register GREG4 bit 4 and bit 6 and may take on the following state, see Table 57 below. Table 57. Asserted Value and Deasserted State for GREG4 Bit 4 and Bit 6 Logic Combinations Greg4 Bit 4 0 1 0 1 Bit 6 0 0 1 1 Interrupt (Pin AD-8) Asserted Value High High Low Low Deasserted Value Low 3-state High 3-state -- Wired-OR -- Wired-AND Functionality
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Register Architecture
Table 58 is an overview of the register architecture. The table is a summary of the register function and address. Complete detail of each register is given in the following sections. Table 58. Register Summary Register Function Register Address (hex)* Channel 1--8 Global Registers GREG0 GREG1 GREG2 GREG3 GREG4 GREG5 GREG6 GREG7 GREG8 GREG9 Framer Block Interrupt Status Framer Block Interrupt Enable FDL Block Interrupt Status FDL Block Interrupt Enable Global Control Device ID and Version Device ID and Version Device ID and Version Global Control Global PLLCK Control Framer Registers Status Registers FRM_SR0 FRM_SR1 FRM_SR2 FRM_SR3 FRM_SR4 FRM_SR5 FRM_SR6 FRM_SR7 FRM_SR8, FRM_SR9 FRM_SR10, FRM_SR11 FRM_SR12, FRM_SR13 FRM_SR14, FRM_SR15 FRM_SR16, FRM_SR17 FRM_SR18, FRM_SR19 FRM_SR20, FRM_SR21 Interrupt Status Facility Alarm Condition Remote End Alarm Facility Errored Event Facility Event Exchange Termination and Exchange Termination Remote End Interface Status Network Termination and Network Termination Remote End Interface Status Facility Event Bipolar Violation Counter Framing Bit Error Counter CRC Error Counter E-bit Counter CRC-4 Error at NT1 from NT2 Counter E-bit at NT1 from NT2 Counter ET Errored Seconds Counter Y00 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08, Y09 Y0A, Y0B Y0C, Y0D Y0E, Y0F Y10, Y11 Y12, Y13 Y14, Y15 000 001 002 003 004 005 006 007 008 009
* The most significant digit, designated by Y, is used to identify each framer (for framer 1--framer 8, Y = 2--9, respectively).
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Register Architecture (continued)
Table 58. Register Summary (continued) Register Function Register Address (hex)* Channel 1--8 Framer Registers (continued) Status Registers (continued) FRM_SR22, FRM_SR23 FRM_SR24, FRM_SR25 FRM_SR26, FRM_SR27 FRM_SR28, FRM_SR29 FRM_SR30, FRM_SR31 FRM_SR32, FRM_SR33 FRM_SR34, FRM_SR35 FRM_SR36, FRM_SR37 FRM_SR38, FRM_SR39 FRM_SR40, FRM_SR41 FRM_SR42, FRM_SR43 FRM_SR44, FRM_SR45 FRM_SR46, FRM_SR47 FRM_SR48, FRM_SR49 FRM_SR50, FRM_SR51 FRM_SR52 FRM_SR53 FRM_SR54-- FRM_SR63 ET Bursty Errored Seconds Counter ET Severely Errored Seconds Counter ET Unavailable Seconds Counter ET-RE Errored Seconds Counter ET-RE Bursty Errored Seconds Counter ET-RE Severely Errored Seconds Counter ET-RE Unavailable Seconds Counter NT1 Errored Seconds Counter NT1 Bursty Errored Seconds Counter NT1 Severely Errored Seconds Counter NT1 Unavailable Seconds Counter NT1-RE Errored Seconds Counter NT1-RE Bursty Errored Seconds Counter NT1-RE Severely Errored Seconds Counter NT1-RE Unavailable Seconds Counter Receive NOT-FAS TS0 Received Sa SLC-96 FDL/CEPT Sa Receive Stack Y16, Y17 Y18, Y19 Y1A, Y1B Y1C, Y1D Y1E, Y1F Y20, Y21 Y22, Y23 Y24, Y25 Y26, Y27 Y28, Y29 Y2A, Y2B Y2C, Y2D Y2E, Y2F Y30, Y31 Y32, Y33 Y34 Y35 Y36--Y3F
Received Signaling Registers FRM_RSR0-- Received Signaling FRM_RSR31 Y40--Y5F
* The most significant digit, designated by Y, is used to identify each framer (for framer 1--framer 8, Y = 2--9, respectively).
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Register Architecture (continued)
Table 58. Register Summary (continued) Register Function Register Address (hex)* Channel 1--8 Framer Registers (continued) Parameter/Control Registers FRM_PR0-- FRM_PR7 FRM_PR8 FRM_PR9 FRM_PR10 FRM_PR11 FRM_PR12, FRM_PR13 FRM_PR14 FRM_PR15 FRM_PR16 FRM_PR17, FRM_PR18 FRM_PR19 FRM_PR20 FRM_PR21 FRM_PR22 FRM_PR23 FRM_PR24 FRM_PR25 FRM_PR26 FRM_PR27 Interrupt Group Enable Framer Mode Option Framer CRC Control Option Alarm Filter Errored Second Threshold Severely Errored Second Threshold Errored Event Enable ET Remote End Errored Event Enable NT1 Errored Event Enable NT1 Remote End Errored Event Enable Y60--Y67 Y68 Y69 Y6A Y6B Y6C, Y6D Y6E Y6F Y70 Y71, Y72 Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y7A Y7B Y7C Y7D Y7E Y7F--Y88 Y89 Y8A Y8B Y8C Y8D Y8E Y8F Y90
Automatic AIS to the System and Automatic Loopback Enable Transmit to the Line Command Framer FDL Loopback Transmission Codes Command Framer Transmit Line Idle Code Framer Transmit System Idle Code Primary Loopback Control Secondary Loopback Control System Frame Sync Mask Source Transmission of Remote Frame Alarm and CEPT Automatic Transmission of A bit = 1 Control FRM_PR28 CEPT Automatic Transmission of E bit = 0 FRM_PR29 Sa4--Sa8 Source FRM_PR30 Sa4--Sa8 Control FRM_PR31-- Sa Transmit Stack/SLC-96 Transmit Stack FRM_PR40 FRM_PR41 Si-bit Source FRM_PR42 Frame Exercise FRM_PR43 System Interface Control FRM_PR44 Signaling Mode FRM_PR45 CHI Common Control FRM_PR46 CHI Common Control FRM_PR47 CHI Transmit Control FRM_PR48 CHI Receive Control
* The most significant digit, designated by Y, is used to identify each framer (for framer 1--framer 8, Y = 2--9, respectively).
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Register Architecture (continued)
Table 58. Register Summary (continued) Register Function Register Address (hex)* Channel 1--8 Framer Registers (continued) Parameter/Control Registers (continued) FRM_PR49-- FRM_PR52 FRM_PR53-- FRM_PR56 FRM_PR57-- FRM_PR60 FRM_PR61-- FRM_PR64 FRM_PR65 FRM_PR66 FRM_PR69 FRM_PR70 Transmit CHI Time-Slot Enable Receive CHI Time-Slot Enable CHI Transmit Highway Select CHI Receive Highway Select CHI Transmit Control CHI Receive Control Auxiliary Pattern Generator Control Auxiliary Pattern Detector Control Y91--Y94 Y95--Y98 Y99--Y9C Y9D--YA0 YA1 YA2 YA5 YA6 YE0--YF7 Facility Data Link Registers FDL Parameter/Control Registers Register Address (hex) FDL 1 FDL 3 FDL 5 FDL 7 FDL_PR0 FDL_PR1 FDL_PR2 FDL_PR3 FDL_PR4 FDL_PR5 FDL_PR6 FDL_PR7 FDL_PR8 FDL_PR9 FDL_PR10 FDL_SR0 FDL_SR1 FDL_SR2 FDL_SR3 FDL_SR4 FDL Configuration Control FDL Control FDL Interrupt Mask Control FDL Transmitter Configuration Control FDL Transmitter FIFO FDL Transmitter Mask FDL Receive Interrupt Level Control Not Assigned FDL Receive Match Character FDL Transparent Control FDL Transmit ANSI ESF Bit Codes FDL Interrupt Status FDL Transmitter Status FDL Receiver Status FDL ANSI Bit Codes Status FDL Receive FIFO Y00 Y01 Y02 Y03 Y04 Y05 Y06 -- Y08 Y09 Y0A Y0B Y0C Y0D Y0E Y07 FDL 2 FDL 4 FDL 6 FDL 8 Y20 Y21 Y22 Y23 Y24 Y25 Y26 -- Y28 Y29 Y2A Y2B Y2C Y2D Y2E Y27
Transmit Signaling Registers FRM_TSR0-- Transmit Signaling FRM_TSR31
FDL Status Registers
* The most significant digit, designated by Y, is used to identify each framer (for framer 1--framer 8, Y = 2--9, respectively). For FDL 1 and FDL 2, Y = A; for FDL 3 and FDL 4, Y = B; for FDL 5 and FDL 6, Y = C; for FDL 7 and FDL 8, Y = D.
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TFRA08C13 OCTAL T1/E1 Framer
Global Register Architecture
REGBANK0 contains the status and programmable control registers for all global functions. The address of these registers is 000 (hex) to 009 (hex). These registers control the eight channels of the TFRA08C13. The register bank architecture is shown in Table 59. The register bank consists of 8-bit registers classified as primary block interrupt status register, primary block interrupt enable register, global loopback control register, global terminal control register, device identification register, and global internal interface control register. Table 59. Global Register Set (0x000--0x009) Global Register Address (hex) 000 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
001 002 003 004
005 006 007 008 009
FRMR8_I FRMR7_I FRMR6_I FRMR5_I FRMR4_I FRMR3_I NT NT NT NT NT NT (0) (0) (0) (0) (0) (0) FRMR8IE FRMR7IE FRMR6IE FRMR5IE FRMR4IE FRMR3IE (0) (0) (0) (0) (0) (0) FDL8_INT FDL7_INT FDL6_INT FDL5_INT FDL4_INT FDL3_INT (0) (0) (0) (0) (0) (0) FDL8IE FDL7IE FDL6IE FDL5IE FDL4E FDL3IE (0) (0) (0) (0) (0) (0) Reserved IPC Reserved ITSC Reserved SECCTRL (0) (0) (0) (0) (0) 0 (0) 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved DIVMUX0 DIVMUX1 DIVMUX2 Reserved LOMUX0 (0) (0) (0) (0) (0) (0) EIPLLCK8 EIPLLCK7 EIPLLCK6 EIPLLCK5 EIPLLCK4 EIPLLCK3 (0) (0) (0) (0) (0) (0)
FRMR2_I NT (0) FRMR2IE (0) FDL2_INT (0) FDL2IE (0) SECCTRL 1 (0) 0 1 0 LOMUX1 (0) EIPLLCK2 (0)
FRMR1_I NT (0) FRMR1IE (0) FDL1_INT (0) FDL1IE (0) SECCTRL 2 (0) 0 1 1 LOMUX2 (0) EIPLLCK1 (0)
* The following section describes the global registers inTable 60--Table 67.
Global Register Structure
Framer Block Interrupt Status Register (GREG0)
A bit set to 1 indicates the block has recently generated an interrupt. This register is cleared on read. Table 60. Framer Block Interrupt Status Register (GREG0) (000) Bit 0 1 2 3 4 5 6 7 Symbol FRMR1_INT FRMR2_INT FRMR3_INT FRMR4_INT FRMR5_INT FRMR6_INT FRMR7_INT FRMR8_INT Description Framer 1 Interrupt. A 1 indicates framer 1 generated an interrupt. Framer 2 Interrupt. A 1 indicates framer 2 generated an interrupt. Framer 3 Interrupt. A 1 indicates framer 3 generated an interrupt. Framer 4 Interrupt. A 1 indicates framer 4 generated an interrupt. Framer 5 Interrupt. A 1 indicates framer 5 generated an interrupt. Framer 6 Interrupt. A 1 indicates framer 6 generated an interrupt. Framer 7 Interrupt. A 1 indicates framer 7 generated an interrupt. Framer 8 Interrupt. A 1 indicates framer 8 generated an interrupt. 123
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Global Register Structure (continued)
Framer Block Interrupt Enable Register (GREG1)
This register enables the individual blocks to assert the interrupt pin high. Table 61. Framer Block Interrupt Enable Register (GREG1) (001) Bit 0 1 2 3 4 5 6 7 Symbol FRMR1IE FRMR2IE FRMR3IE FRMR4IE FRMR5IE FRMR6IE FRMR7IE FRMR8IE Description Framer 1 Interrupt Enable. A 1 enables framer 1 interrupts. Framer 2 Interrupt Enable. A 1 enables framer 2 interrupts. Framer 3 Interrupt Enable. A 1 enables framer 3 interrupts. Framer 4 Interrupt Enable. A 1 enables framer 4 interrupts. Framer 5 Interrupt Enable. A 1 enables framer 5 interrupts. Framer 6 Interrupt Enable. A 1 enables framer 6 interrupts. Framer 7 Interrupt Enable. A 1 enables framer 7 interrupts. Framer 8 Interrupt Enable. A 1 enables framer 8 interrupts.
FDL Block Interrupt Status Enable Register (GREG2)
Table 62. FDL Block Interrupt Status Register (GREG2) (002) Bit 0 1 2 3 4 5 6 7 Symbol FDL1_INT FDL2_INT FDL3_INT FDL4_INT FDL5_INT FDL6_INT FDL7_INT FDL8_INT Description Facility Data Link 1 Interrupt. A 1 indicates FDL1 generated an interrupt. Facility Data Link 2 Interrupt. A 1 indicates FDL2 generated an interrupt. Facility Data Link 3 Interrupt. A 1 indicates FDL3 generated an interrupt. Facility Data Link 4 Interrupt. A 1 indicates FDL4 generated an interrupt. Facility Data Link 5 Interrupt. A 1 indicates FDL5 generated an interrupt. Facility Data Link 6 Interrupt. A 1 indicates FDL6 generated an interrupt. Facility Data Link 7 Interrupt. A 1 indicates FDL7 generated an interrupt. Facility Data Link 8 Interrupt. A 1 indicates FDL8 generated an interrupt.
FDL Block Interrupt Enable Register (GREG3)
This register enables the individual blocks to assert the interrupt pin high. Table 63. FDL Block Interrupt Enable Register (GREG3) (003) Bit 0 1 2 3 4 5 6 7 Symbol FDL1IE FDL2IE FDL3IE FDL4IE FDL5IE FDL6IE FDL7IE FDL8IE Description Facility Data Link 1 Interrupt Enable. Facility Data Link 2 Interrupt Enable. Facility Data Link 3 Interrupt Enable. Facility Data Link 4 Interrupt Enable. Facility Data Link 5 Interrupt Enable. Facility Data Link 6 Interrupt Enable. Facility Data Link 7 Interrupt Enable. Facility Data Link 8 Interrupt Enable. A 1 enables FDL 1 interrupts. A 1 enables FDL 2 interrupts. A 1 enables FDL 3 interrupts. A 1 enables FDL 4 interrupts. A 1 enables FDL 5 interrupts. A 1 enables FDL 6 interrupts. A 1 enables FDL 7 interrupts. A 1 enables FDL 8 interrupts.
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TFRA08C13 OCTAL T1/E1 Framer
Global Register Structure (continued)
Global Control Register (GREG4)
This register selects the source of the output second pulse (bit 0--bit 2), interrupt 3-state control (bit 4), and interrupt polarity (bit 6). Table 64. Global Control Register (GREG4) (004) Bit 0 1 2 Symbol Description
3 4
5 6 7
SECCTRL2 Second Output Control. These bits determine which framer is used to source the output SECCTRL1 SECOND pin: Bit 0 Bit 1 Bit 2 SECCTRL0 0 0 0: FRAMER 1 sources the SECOND pin. 0 0 1: FRAMER 2 sources the SECOND pin. 0 1 0: FRAMER 3 sources the SECOND pin. 0 1 1: FRAMER 4 sources the SECOND pin. 1 0 0: FRAMER 5 sources the SECOND pin. 1 0 1: FRAMER 6 sources the SECOND pin. 1 1 0: FRAMER 7 sources the SECOND pin. 1 1 1: FRAMER 8 sources the SECOND pin. Reserved. -- INTERRUPT 3-State Control. This bit along with bit 6 in this register (polarity control) ITSC allows the interrupt pin to be programmed for active HIGH, active LOW, wire-OR, or wireAND operation, as described below: Bit 4 Bit 6 0 0 Programs the interrupt pin to be active HIGH (1-state) when there is an interrupt condition and to be inactive LOW (0-state) when the condition goes away. 0 1 Programs the interrupt pin to be active LOW (0-state) when there is an interrupt condition and to be inactive HIGH (1-state) when the condition goes away. 1 0 Programs the interrupt pin to be active HIGH (1-state) when there is an interrupt condition and to be inactive HIGH-Z (3-state) when the condition goes away. 1 1 Programs the interrupt pin to be active LOW (0-state) when there is an interrupt condition and to be inactive HIGH-Z (3-state) when the condition goes away. Reserved. -- Interrupt Polarity Control. A 1 inverts the polarity of the interrupt pin (negative polarity). IPC Reserved. --
Device ID and Version Registers (GREG5--GREG7)
These bits define the device and version number of this framer circuit. Table 65. Device ID and Version Registers (GREG5--GREG7) (005--007) Register Device Code Device Code Version # GREG5 GREG6 GREG7 Bit 7 1 0 0 Bit 6 1 0 0 Bit 5 1 0 0 Bit 4 1 0 0 Bit 3 1 0 0 Bit 2 0 0 0 Bit 1 0 1 1 Bit 0 0 1 0
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Global Register Structure (continued)
Global Control Register (GREG8)
Table 66. Global Control Register (GREG8) (008) Bit 0 1 2 Symbol LOMUX2 LOMUX1 LOMUX0 Description Loss of Clock Output Control. These bits determine which framer is used to source the output LORLCK and LOPLLCK pin: Bit 0 Bit 1 Bit 2 0 0 0: FRAMER 1 sources the LORLCK and LOPLLCK pins. 0 0 1: FRAMER 2 sources the LORLCK and LOPLLCK pins. 0 1 0: FRAMER 3 sources the LORLCK and LOPLLCK pins. 0 1 1: FRAMER 4 sources the LORLCK and LOPLLCK pins. 1 0 0: FRAMER 5 sources the LORLCK and LOPLLCK pins. 1 0 1: FRAMER 6 sources the LORLCK and LOPLLCK pins. 1 1 0: FRAMER 7 sources the LORLCK and LOPLLCK pins. 1 1 1: FRAMER 8 sources the LORLCK and LOPLLCK pins. Reserved. Divide Clocks Output Control. These bits determine which framer is used to source the output DIV-RLCK, DIV-PLLCK, DIV-CHICK, CHICK-EPLL, and PLLCK-EPLL pins: Bit 0 Bit 1 Bit 2 0 0 0: FRAMER 1 sources the DIV-RLCK, DIV-PLLCK, DIV-CHICK, CHICK-EPLL and PLLCK-EPLL pins. 0 0 1: FRAMER 2 sources the DIV-RLCK, DIV-PLLCK, DIV-CHICK, CHICK-EPLL and PLLCK-EPLL pins. 0 1 0: FRAMER 3 sources the DIV-RLCK, DIV-PLLCK, DIV-CHICK, CHICK-EPLL and PLLCK-EPLL pins. 0 1 1: FRAMER 4 sources the DIV-RLCK, DIV-PLLCK, DIV-CHICK, CHICK-EPLL and PLLCK-EPLL pins. 1 0 0: FRAMER 5 sources the DIV-RLCK, DIV-PLLCK, DIV-CHICK, CHICK-EPLL and PLLCK-EPLL pins. 1 0 1: FRAMER 6 sources the DIV-RLCK, DIV-PLLCK, DIV-CHICK, CHICK-EPLL and PLLCK-EPLL pins. 1 1 0: FRAMER 7 sources the DIV-RLCK, DIV-PLLCK, DIV-CHICK, CHICK-EPLL and PLLCK-EPLL pins. 1 1 1: FRAMER 8 sources the DIV-RLCK, DIV-PLLCK, DIV-CHICK, CHICK-EPLL and PLLCK-EPLL pins. Reserved.
3 4 5 6
-- DIVMUX2 DIVMUX1 DIVMUX0
7
--
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TFRA08C13 OCTAL T1/E1 Framer
Global Register Structure (continued)
Global PLLCK Control Register (GREG9)
This register selectively enables/disables an individual transmit framer's internal clock synthesizer. setting all bits to 0 (the default condition) disables all transmit framer clock synthesizers, and allows an external source of PLLCK to drive the transmit framers. Table 67. Global PLLCK Control Register (GREG9) (009) Bit 0 1 2 3 4 5 6 7 Symbol EIPLLCK1 EIPLLCK2 EIPLLCK3 EIPLLCK4 EIPLLCK5 EIPLLCK6 EIPLLCK7 EIPLLCK8 Description Enable Transmit Framer 1's Internal PLLCK Clock Synthesizer. Enable Transmit Framer 2's Internal PLLCK Clock Synthesizer. Enable Transmit Framer 3's Internal PLLCK Clock Synthesizer. Enable Transmit Framer 4's Internal PLLCK Clock Synthesizer. Enable Transmit Framer 5's Internal PLLCK Clock Synthesizer. Enable Transmit Framer 6's Internal PLLCK Clock Synthesizer. Enable Transmit Framer 7's Internal PLLCK Clock Synthesizer. Enable Transmit Framer 8's Internal PLLCK Clock Synthesizer.
Framer Register Architecture
REGBANK1--REGBANK8 contain the status and programmable control registers for the framer and system CHI interface channels FRM1--FRM8. The base address for REGBANK1--REGBANK8 is Y00 (hex), where Y = 2--9 for FRM1--FRM8, respectively. Within these register banks, the bit map is identical for FRM1--FRM8. The framer registers are structures as shown in Table 68. Default values are given in the individual register definition tables. Table 68. Framer Status and Control Blocks Address Range (Hexadecimal) Framer Register Block Status Registers (COR) (Y00--Y3F)* Receive Signaling Registers (Y40--Y5F)* Parameter (Configuration) Registers (Y60--YA6)* Transmit Signaling Registers (YE0--YFF)*
* The most significant digit, designated by Y, is used to identify each framer (for framer 1--framer 8, Y = 2--9, respectively).
All status registers are clocked with the internal framer receive line clock (RFRMCK). Bits in status registers FRM_SR1 and FRM_SR7 are set at the onset of the condition and are cleared on read when the given condition is no longer present. These registers can generate interrupts if the corresponding register bits are enabled in interrupt enable registers FRM_PR0--FRM_PR7. On all 16-bit counter registers (FRM_SR8-- FRM_SR51), both bytes are cleared only after reading both bytes. These status registers are two byte register pairs. These register pairs must be read in succession, with the lower byte read first followed by a read of higher byte. Once a read is initiated on one of the bytes, the updating of that counter is disabled and remains disabled until both bytes are read. All events during this interval are lost. Updating of the counter registers is stopped when all of the bits are set to 1. Updating resumes after the registers are cleared on read. These register pairs may be read in any order, but they must be read in pairs, i.e., a read of 1 byte must be followed immediately by a read of the remaining byte of the pair. Status registers FRM_SR0--FRM_SR63 are clear-onread (COR) registers. These registers are cleared by the framer internal received line clock (RFRMCK). At least two RFRMCK cycles (1.3 s for DS1 and 1.0 s for CEPT) must be allowed between successive reads of the same COR register to allow it to properly clear.
The complete register map for the framer is given in Table 182--Table 186. The address of the registers is shown in the table title with the most significant digit, designated by Y, used to identify each framer (for framer 1--framer 8, Y = 2--9, respectively).
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Framer Register Architecture (continued)
Framer Status/Counter Registers
Registers FRM_SR0--FRM_SR63 report the status of each framer. All are clear-on-read, read-only registers. Interrupt Status Register (FRM_SR0) The interrupt pin (INTERRUPT) goes active when a bit in this register and its associated interrupt enable bit in registers FRM_PR0--FRM_PR7 are set, and the interrupt for the framer block is enabled in register GREG1. Table 69. Interrupt Status Register (FRM_SR0) (Y00) Bit 0 1 2 3 4 5 6 7 Symbol FAC RAC FAE ESE TSSFE RSSFE -- S96SR Description Facility Alarm Condition. A 1 indicates a facility alarm occurred (go read FRM_SR1). Remote Alarm Condition. A 1 indicates a remote alarm occurred (go read FRM_SR2). Facility Alarm Event. A 1 indicates a facility alarm occurred (go read FRM_SR3 and FRM_SR4). Errored Second Event. A 1 indicates an errored second event occurred (go read FRM_SR5, FRM_SR6, and FRM_SR7). Transmit Signaling Superframe Event. A 1 indicates that a MOS superframe block has been transmitted and the transmit signaling data buffers are ready for new data. Receive Signaling Superframe Event. A 1 indicates that a MOS superframe block has been received and the receive signaling data buffers must be read. Reserved. SLC-96 Stack Ready. A 1 indicates that either the transmit framer SLC-96 stack is ready for more data or the receive framer SLC-96 stack contains new data.
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
Facility Alarm Condition Register (FRM_SR1) The bits in the facility alarm condition register (FRM_SR1) indicate alarm state of the receive framer section. Interrupts from this register are generated once at the onset of the alarm condition. If the alarm condition is still present at the time of the read, the bit will remain in the 1 state for the duration of the alarm condition. If the alarm condition is no longer present at the time of the read, then the bit is cleared on read. Table 70. Facility Alarm Condition Register (FRM_SR1) (Y01) Bit 0 1 Symbol LFA LSFA Description Loss of Frame Alignment. A 1 indicates the receive framer is in a loss of frame alignment and is currently searching for a new alignment. Loss of Signaling Superframe Alignment. A 1 indicates the receive framer is in a loss of signaling superframe alignment in the DS1 framing formats. A search for a new signaling superframe alignment starts once frame alignment is established. Loss of Time Slot 16 Signaling Multiframe Alignment. A 1 indicates the receive framer is in a loss of time slot 16 signaling multiframe alignment in the CEPT mode. A search for a new time slot 16 signaling multiframe alignment starts once frame alignment is established. This bit is 0 when the TFRA08C13 is programmed for the transparent signaling mode, register FRM_PR44 bit 0 (TSIG) = 1. Loss of Transmit Superframe Alignment. A 1 indicates superframe alignment pattern in the transmit facility data link as defined for SLC-96 is lost. Only valid for SLC-96 mode. This bit is 0 in all other DS1 modes. Loss of Time Slot 0 CRC-4 Multiframe Alignment. A 1 indicates an absence of CRC-4 multiframe alignment after initial basic frame alignment is established. A 0 indicates either CRC-4 checking is disabled or CRC-4 multiframe alignment has been successfully detected. Loss of Frame Alignment Since Last Read. A 1 indicates that the LFA state indicated in bit 0 of this register is the same LFA state as the previous read. Loss of Biframe Alignment. A 1 indicates that the CEPT biframe alignment pattern (alternating 10 in bit 2 of time slot 0 of each frame) in the receive system data is errored. This alignment pattern is required when transmitting the Si or Sa bits transparently. Only valid in the CEPT mode. This bit is 0 in all other modes. Receive Time Slot 16 Alarm Indication Signal. A 1 indicates the receive framer detected time slot 16 AIS in the CEPT mode. This bit is 0 in the DS1 modes. Auxiliary Pattern. A 1 indicates the detection of a valid AUXP (unframed 1010 . . . pattern) in the CEPT mode. This bit is 0 in the DS1 modes. Alarm Indication Signal. A 1 indicates the receive framer is currently receiving an AIS pattern from its remote line end.
LTS16MFA
2
LTSFA
LTS0MFA
3 4
LFALR LBFA
5 6 7
RTS16AIS AUXP AIS
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Framer Register Architecture (continued)
Remote End Alarm Register (FRM_SR2) A bit set to 1 indicates the receive framer has recently received the given alarm. Interrupts from this register are generated once at the beginning of the alarm condition. If the alarm is still present at the time of the read, the bit will remain in the 1 state for the duration of the alarm condition. If the alarm condition is no longer present at the time of the read, then the bit is cleared on read. Table 71. Remote End Alarm Register (FRM_SR2) (Y02) Bit 0 1 Symbol RFA RJYA RTS16MFA 2 3 4 5 6 7 CREBIT Sa6 = 8 Sa6 = A Sa6 = C Sa6 = E Sa6 = F Description Remote Framer Alarm. A 1 indicates the receive framer detected a remote frame (yellow) alarm. Remote Japanese Yellow Alarm. A 1 indicates the receive framer detected the Japanese format remote frame alarm. Remote Multiframe Alarm. A 1 indicates the receive framer detected a time slot 16 remote frame alarm in the CEPT mode. Continuous Received E Bits. A 1 indicates the detection of a five-second interval containing 991 E bit = 0 events in each second. This bit is 0 in the DS1 mode. Received Sa6 = 8. A 1 indicates the receive framer detected an Sa6 code equal to 1000. This bit is 0 in the DS1 mode. Received Sa6 = A. A 1 indicates the receive framer detected an Sa6 code equal to 1010. This bit is 0 in the DS1 mode. Received Sa6 = C. A 1 indicates the receive framer detected an Sa6 code equal to 1100. This bit is 0 in the DS1 mode. Received Sa6 = E. A 1 indicates the receive framer detected an Sa6 code equal to 1110. This bit is 0 in the DS1 mode. Received Sa6 = F. A 1 indicates the receive framer detected an Sa6 code equal to 1111. This bit is 0 in the DS1 mode.
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
Facility Errored Event Register (FRM_SR3) A bit set to 1 indicates the receive framer has recently received the given errored event. Table 72. Facility Errored Event Register-1 (FRM_SR3) (Y03) Bit 0 1 2 3 Symbol LFV FBE CRCE ECE Description Line Format Violation. A 1 indicates the receive framer detected a bipolar line coding or excessive zeros violation. Frame-Bit Errored. A 1 indicates the receive framer detected a frame-bit or frame alignment pattern error. CRC Errored. A 1 indicates the receive framer detected CRC errors. Excessive CRC Errors. A 1 indicates the receive framer detected an excessive CRC errored condition. This bit is only valid in the ESF and CEPT with CRC-4 modes; otherwise, it is 0. Received E Bit = 0. A 1 indicates the receive framer detected an E bit = 0 in either frame 13 or 15 of the time slot 0 of CRC-4 multiframe. This bit is 0 in the DS1 modes. Lack of CRC-4 Multiframe Alignment Timer Expire Indication. A 1 indicates that either the 100 ms or the 400 ms CRC-4 interworking timer expired. Active only immediately after establishment of the initial basic frame alignment. This bit is 0 in the DS1 modes. Receive Elastic Store Slip: Buffer Overflow. A 1 indicates the receive elastic store performed a control slip due to an elastic buffer overflow condition. Receive Elastic Store Slip: Buffer Underflow. A 1 indicates the receive elastic store performed a control slip due to an elastic buffer underflow condition.
4 5
REBIT LCRCATMX
6 7
SLIPO SLIPU
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Framer Register Architecture (continued)
Table 73. Facility Event Register-2 (FRM_SR4) (Y04) Bit 0 1 Symbol NFA Description
2
3
4
5
New Frame Alignment. A 1 indicates the receive framer established a new frame alignment which differs from the previous alignment. Signaling Superframe Alignment. A 1 indicates the receive framer has established the SSFA signaling superframe alignment. In the SF modes (D4 and SLC-96) and CEPT modes, this alignment is established only after primary frame alignment is determined. T1 Line Loopback Off Code Detect. A 1 indicates the receive framer detected the DS1 LLBOFF line loopback disable code in the payload. This code is defined in AT&T Technical Reference 62411 as a framed 001 pattern where the frame bit is inserted into the pattern. New Biframe Alignment Established. A 1 indicates the transmit framer has established BFA a biframe alignment for the transmission of transparent Si and or Sa bits from the system data in the CEPT mode. T1 Line Loopback On Code Detect. A 1 indicates the receive framer detected the line LLBON loopback enable code in the payload. This code is defined in AT&T Technical Reference 62411 as a framed 00001 pattern where the frame bit is inserted into the pattern. New CEPT CRC-4 Multiframe Alignment. A 1 indicates the CEPT CRC-4 multiframe CMA alignment in the receive framer has been established. FDL-PLBON ESF FDL Payload Loopback On Code Detect. A 1 indicates the receive framer detected the line loopback enable code in the payload. This code is defined in ANSI T1.403-1995 as a 1111111100101000 pattern in the facility data link, where the leftmost bit is the MSB. SLC-96 Receive FDL Stack Ready. A 1 indicates that the receive FDL stack should be SLCRFSR read. This bit is cleared on read. Data in the receive FIFO must be read within 9 ms of this interrupt. This bit is not updated during loss of frame or signaling superframe alignment. FDL-PLBOFF ESF FDL Payload Loopback Off Code Detect. A 1 indicates the receive framer detected the line loopback disable code in the payload. This code is defined in ANSI T1.403-1995 as a 1111111101001100 pattern in the facility data link, where the leftmost bit is the MSB.
6
7
SLC-96 Transmit FDL Stack Ready. A 1 indicates that the transmit FDL stack is ready for new data. This bit is cleared on read. Data written within 9 ms of this interrupt will be transmitted in the next SLC-96 D-bit superframe interval. FDL-LLBON ESF FDL Line Loopback On Code Detect. A 1 indicates the receive framer detected the line loopback enable code in the payload. This code is defined in ANSI T1.403-1995 as a 1111111101110000 pattern in the facility data link, where the leftmost bit is the MSB. CEPT Receive Sa Stack Ready. A 1 indicates that the receive Sa6 stack should be RSaSR read. This bit is clear on the first access to the Sa receive stack or at the beginning of frame 0 of the CRC-4 double-multiframe. Data in the receive FIFO must be read within 4 ms of this interrupt. This bit is not updated during LFA. FDL-LLBOFF ESF FDL Line Loopback Off Code Detect. A 1 indicates the receive framer detected the line loopback disable code in the payload. This code is defined in ANSI T1.403-1995 as a 1111111100011100 pattern in the facility data link, where the leftmost bit is the MSB. CEPT Transmit Sa Stack Ready. A 1 indicates that the transmit Sa stack is ready for TSaSR new data. This bit is cleared on the first access to the Sa transmit stack or at the beginning of frame 0 of the CRC-4 double multiframe. Data written within 4 ms of this interrupt will be transmitted in the next CRC-4 double multiframe interval. SLCTFSR
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
The following registers are dedicated to the exchange termination and its remote end interface. The alarm conditions to trigger errored seconds and severely errored seconds are defined in Table 32 and the ET and ET-RE enable registers, FRM_PR14 and FRM_PR15. The thresholds are defined in registers FRM_PR11--FRM_PR13. Table 74. Exchange Termination and Exchange Termination Remote End Interface Status Register (FRM_SR5) (Y05) Bit 0 1 2 3 Symbol ETES ETBES ETSES ETUAS Description ET Errored Second. A 1 indicates the receive framer detected an errored second at the exchange termination (ET). ET Bursty Errored Second. A 1 indicates the receive framer detected a bursty errored second at the ET. ET Severely Errored Second. A 1 indicates the receive framer detected a severely errored second at the ET. ET Unavailable State. A 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. Upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is used resulting in a ten-second delay in the reporting of this condition. ET-RE Errored Second. A 1 indicates the receive framer detected an errored second at the exchange termination remote end (ET-RE). ET-RE Bursty Errored Second. A 1 indicates the receive framer detected a bursty errored second at the ET-RE. ET-RE Severely Errored Second. A 1 indicates the receive framer detected a severely errored second at the ET-RE. ET-RE Unavailable State. A 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. Upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is used resulting in a ten-second delay in the reporting of this condition.
4 5 6 7
ETREES ETREBES ETRESES ETREUAS
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Framer Register Architecture (continued)
The following status registers are dedicated to the NT1 and the NT1 remote end (NT1-RE) interface. The alarm conditions to evaluate errored seconds and severely errored seconds are defined in Table 32 and the NT1 and NT1-RE enable registers, FRM_PR16--FRM_PR18. The thresholds are defined in registers FRM_PR11-- FRM_PR13. Table 75. Network Termination and Network Termination Remote End Interface Status Register (FRM_SR6) (Y06) Bit 0 1 2 3 Symbol NTES NTBES NTSES NTUAS Description NT Errored Second. A 1 indicates the receive framer detected an errored second at the network termination (NT). NT Bursty Errored Second. A 1 indicates the receive framer detected a bursty errored second at the NT. NT Severely Errored Second. A 1 indicates the receive framer detected a severely errored second at the NT. NT Unavailable State. A 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. Upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is used resulting in a ten-second delay in the reporting of this condition. NT-RE Errored Second. A 1 indicates the receive framer detected an errored second at the exchange termination remote end (ET-RE). NT-RE Bursty Errored Second. A 1 indicates the receive framer detected a bursty errored second at the ET-RE. NT-RE Severely Errored Second. A 1 indicates the receive framer detected a severely errored second at the NT-RE. NT-RE Unavailable State. A 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. Upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. ITU Recommendation G.826 is used resulting in a ten-second delay in the reporting of this condition.
4 5 6 7
NTREES NTREBES NTRESES NTREUAS
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
Bit 0--bit 4 in this register are set high when the receive framer comes out of the unavailable state, while bit 4--bit 7 report detection of the receive test patterns. Bits 4 and 5 are cleared only after register FRM_PR70 bit 2 is set to 0. Table 76. Facility Event Register (FRM_SR7) (Y07) Bit 0 1 Symbol OUAS EROUAS Description Out of Unavailable State. A 1 indicates the receive framer detected ten consecutive seconds that were not severely errored while in the unavailable state at the ET. Out of Unavailable State at the ET-RE. A 1 indicates the receive framer detected ten consecutive seconds that were not severely errored while in the unavailable state at the ET-RE. Out of Unavailable State at the NT1. A 1 indicates the receive framer detected ten consecutive seconds that were not severely errored while in the unavailable state at the NT. Out of Unavailable State NT1-RE. A 1 indicates the receive framer detected ten consecutive seconds that were not severely errored while in the unavailable state at the NTRE. Test Pattern Detected. A 1 indicates the pattern detector has locked onto the pattern specified by the PTRN configuration bits defined in register FRM_PR70. Test Pattern Bit Error. A 1 indicates the pattern detector has found one or more single bit errors in the pattern that it is currently locked onto. Receiving Pseudorandom Pattern. A 1 indicates the receive framer pattern monitor circuit is currently detecting the 215 - 1 pseudorandom pattern*. Receiving Quasi-Random Pattern. A 1 indicates the receive framer pattern monitor circuit is currently detecting the 2 20 - 1 quasi-random pattern*.
2 3
NT1OUAS NROUAS
4 5 6 7
DETECT PTRNBER RPSUEDO RQUASI
* It is possible for one of these bits to be set to 1, if the received line data is all zeros.
Bipolar Violation Counter Register (FRM_SR8--FRM_SR9) This register contains the 16-bit count of received bipolar violations, line code violations, or excessive zeros. Table 77. Bipolar Violation Counter Registers (FRM_SR8--FRM_SR9) (Y08--Y09) Register FRM_SR8 FRM_SR9 Byte MSB LSB Bit 7--0 7--0 Symbol BPV15--BPV8 BPV7--BPV0 BPVs Counter. BPVs Counter. Description
Frame Bit Errored Counter Register (FRM_SR10--FRM_SR11) This register contains the 16-bit count of framing bit errors. Framing bit errors are not counted during loss of frame alignment. Table 78. Framing Bit Error Counter Registers (FRM_SR10--FRM_SR11) (Y0A--Y0B) Register FRM_SR10 FRM_SR11 Byte MSB LSB Bit 7--0 7--0 Symbol FBE15--FBE8 FBE7--FBE0 Description Frame Bit Errored Counter. Frame Bit Errored Counter.
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CRC Error Counter Register (FRM_SR12--FRM_SR13) This register contains the 16-bit count of CRC errors. CRC errors are not counted during loss of CRC multiframe alignment. Table 79. CRC Error Counter Registers (FRM_SR12--FRM_SR13) (Y0C--Y0D) Register FRM_SR12 FRM_SR13 Byte MSB LSB Bit 7--0 7--0 Symbol CEC15--CEC8 CEC7--CEC0 CRC Errored Counter. CRC Errored Counter. Description
E-Bit Counter Register (FRM_SR14--FRM_SR15) This register contains the 16-bit count of received E bit = 0 events. E bits are not counted during loss of CEPT CRC-4 multiframe alignment. Table 80. E-Bit Counter Registers (FRM_SR14--FRM_SR15) (Y0E--Y0F) Register FRM_SR14 FRM_SR15 Byte MSB LSB Bit 7--0 7--0 Symbol REC15--REC8 REC7--REC0 E-Bit Counter. E-Bit Counter. Description
CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16--FRM_SR17) This register contains the 16-bit count of each occurrence of Sa6 code 001X, detected synchronously to the CEPT CRC-4 multiframe. Table 81. CRC-4 Errors at NT1 from NT2 Counter Registers (FRM_SR16--FRM_SR17) (Y10--Y11) Register FRM_SR16 FRM_SR17 Byte MSB LSB Bit 7--0 7--0 Symbol CNT15--CNT8 CNT7--CNT0 Description CRC-4 Errors at NT1 Counter. CRC-4 Errors at NT1 Counter.
E Bit at NT1 from NT2 Counter Registers (FRM_SR18--FRM_SR19) This register contains the 16-bit count of each occurrence of Sa6 code 00X1, detected synchronously to the CEPT CRC-4 multiframe. E bits are not counted during loss of CEPT CRC-4 multiframe alignment. Table 82. E Bit at NT1 from NT2 Counter (FRM_SR18--FRM_SR19) (Y12--Y13) Register FRM_SR18 FRM_SR19 Byte MSB LSB Bit 7--0 7--0 Symbol ENT15--ENT8 ENT7--ENT0 E Bit at NT1 Counter. E Bit at NT1 Counter. Description
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
The following status registers, FRM_SR20--FRM_SR51, contain the 16-bit count of errored seconds, bursty errored seconds, severely errored seconds, and unavailable seconds at the ET, ET-RE, NT1, and NT1-RE terminals. DS1 error conditions are reported in the ET Errored Registers FRM_SR20--FRM_SR35. Table 83. ET Errored Seconds Counter (FRM_SR20--FRM_SR21) (Y14--Y15) Register FRM_SR20 FRM_SR21 Byte MSB LSB Bit 7--0 7--0 Symbol ETES15--ETES8 ETES7--ETES0 Description ET Errored Seconds Counter. ET Errored Seconds Counter.
Table 84. ET Bursty Errored Seconds Counter (FRM_SR22--FRM_SR23) (Y16--Y17) Register FRM_SR22 FRM_SR23 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETBES15--ETBES8 ET Bursty Errored Seconds Counter. ETBES7--ETBES0 ET Bursty Errored Seconds Counter.
Table 85. ET Severely Errored Seconds Counter (FRM_SR24--FRM_SR25) (Y18--Y19) Register FRM_SR24 FRM_SR25 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETSES15--ETSES8 ET Severely Errored Seconds Counter. ETSES7--ETSES0 ET Severely Errored Seconds Counter.
Table 86. ET Unavailable Seconds Counter (FRM_SR26--FRM_SR27) (Y1A--Y1B) Register FRM_SR26 FRM_SR27 Byte MSB LSB Bit 7--0 7--0 Symbol ETUS15--ETUS8 ETUS7--ETUS0 Description ET Unavailable Seconds Counter Bits. ET Unavailable Seconds Counter Bits.
Table 87. ET-RE Errored Seconds Counter (FRM_SR28--FRM_SR29) (Y1C--Y1D) Register FRM_SR28 FRM_SR29 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETREES15--ETREES8 ET-RE Errored Seconds Counter. ETREES7--ETREES0 ET-RE Errored Seconds Counter.
Table 88. ET-RE Bursty Errored Seconds Counter (FRM_SR30--FRM_SR31) (Y1E--Y1F) Register FRM_SR30 FRM_SR31 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETREBES15--ETREBES8 ET-RE Bursty Errored Seconds Counter. ETREBES7--ETREBES0 ET-RE Bursty Errored Seconds Counter.
Table 89. ET-RE Severely Errored Seconds Counter (FRM_SR32--FRM_SR33) (Y20--Y21) Register FRM_SR32 FRM_SR33 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETRESES15--ETRESES8 ET-RE Severely Errored Seconds Counter. ETRESES7--ETRESES0 ET-RE Severely Errored Seconds Counter.
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Framer Register Architecture (continued)
Table 90. ET-RE Unavailable Seconds Counter (FRM_SR34--FRM_SR35) (Y22--Y23) Register FRM_SR34 FRM_SR35 Byte MSB LSB Bit 7--0 7--0 Symbol Description
ETREUS15--ETRESES8 ET-RE Unavailable Seconds Counter. ETRESES7--ETRESES0 ET-RE Unavailable Seconds Counter.
Table 91. NT1 Errored Seconds Counter (FRM_SR36--FRM_SR37) (Y24--Y25) Register FRM_SR36 FRM_SR37 Byte MSB LSB Bit 7--0 7--0 Symbol NTES15--NTES8 NTES7--NTES0 Description NT1 Errored Seconds Counter. NT1 Errored Seconds Counter.
Table 92. NT1 Bursty Errored Seconds Counter (FRM_SR38--FRM_SR39) (Y26--Y27) Register FRM_SR38 FRM_SR39 Byte MSB LSB Bit 7--0 7--0 Symbol NTBES15--NTBES8 NTBES7--NTBES0 Description NT1 Bursty Errored Seconds Counter. NT1 Bursty Errored Seconds Counter.
Table 93. NT1 Severely Errored Seconds Counter (FRM_SR40--FRM_SR41) (Y28--Y29) Register FRM_SR40 FRM_SR41 Byte MSB LSB Bit 7--0 7--0 Symbol NTSES15--NTSES8 NTSES7--NTSES0 Description NT1 Severely Errored Seconds Counter. NT1 Severely Errored Seconds Counter.
Table 94. NT1 Unavailable Seconds Counter (FRM_SR42--FRM_SR43) (Y2A--Y2B) Register FRM_SR42 FRM_SR43 Byte MSB LSB Bit 7--0 7--0 Symbol NTUS15--NTUS8 NTUS7--NTUS0 Description NT1 Unavailable Seconds Counter Bits. NT1 Unavailable Seconds Counter Bits.
Table 95. NT1-RE Errored Seconds Counter (FRM_SR44--FRM_SR45) (Y2C--Y2D) Register FRM_SR44 FRM_SR45 Byte MSB LSB Bit 7--0 7--0 Symbol NTREES15--NTREES8 NTREES7--NTREES0 Description NT1-RE Errored Seconds Counter. NT1-RE Errored Seconds Counter.
Table 96. NT1-RE Bursty Errored Seconds Counter (FRM_SR46--FRM_SR47) (Y2E--Y2F) Register FRM_SR46 FRM_SR47 Byte MSB LSB Bit 7--0 7--0 Symbol Description
NTREBES15--NTREBES8 NT1-RE Bursty Errored Seconds Counter. NTREBES7--NTREBES0 NT1-RE Bursty Errored Seconds Counter.
Table 97. NT1-RE Severely Errored Seconds Counter (FRM_SR48--FRM_SR49) (Y30--Y31) Register FRM_SR48 FRM_SR49 Byte MSB LSB Bit 7--0 7--0 Symbol Description
NTRESES15--NTRESES8 NT1-RE Severely Errored Seconds Counter. NTRESES7--NTRESES0 NT1-RE Severely Errored Seconds Counter.
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
Table 98. NT1-RE Unavailable Seconds Counter (FRM_SR50--FRM_SR51) (Y32--Y33) Register FRM_SR50 FRM_SR51 Byte MSB LSB Bit 7--0 7--0 Symbol NTREUS15--NTREUS8 NTREUS7--NTREUS0 Description NT1-RE Unavailable Seconds Counter Bits. NT1-RE Unavailable Seconds Counter Bits.
Received NOT-FAS TS0 RSa Register (FRM_SR52) This register contains the last (since last read) valid received RSa8-- RSa4 bits, A bit, and Si bit of NOT-FAS time slot 0 and the Si bit of FAS time slot 0 while the receive framer was in basic frame alignment. Table 99. Receive NOT-FAS TS0 Register (FRM_SR52) (Y34) Bit 7 NOT-FAS bit 1 (CEPT without CRC-4) or frame 15 E bit (CEPT with CRC-4) Bit 6 FAS bit 1 (CEPT without CRC-4) or frame 13 E bit (CEPT with CRC-4) Bit 5 A bit Bit 4 Sa4 Bit 3 Sa5 Bit 2 Sa6 Bit 1 Sa7 Bit 0 Sa8
Received Sa Register (FRM_SR53) This register contains the last (since last read) valid time slot 16 spare bits of the frame containing the time slot 16 signaling multiframe alignment. These bits are updated only when the receive framer is in signaling multiframe alignment. Table 100. Receive Sa Register (FRM_SR53) (Y35) Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 X2 Bit 1 X1 Bit 0 X0
SLC-96 FDL/CEPT Sa Receive Stack (FRM_SR54--FRM_SR63)
In the SLC-96 frame format, FRM_SR54 through FRM_SR58 contain the received SLC-96 facility data link data block. When the framer is in a loss of frame alignment or loss of signaling superframe alignment, these registers are not updated. Note: The RSP[1:4] are the received spoiler bits. Table 101. SLC-96 FDL Receive Stack (FRM_SR54--FRM_SR63) (Y36--Y3F)
Register FRM_SR54 FRM_SR55 FRM_SR56 FRM_SR57 FRM_SR58 FRM_SR59-- FRM_SR61 Bit 7 0 0 RC1 RC9 RM3 0 Bit 6 0 0 RC2 RC10 RA1 0 Bit 5 R-0 R-0 RC3 RC11 RA2 0 Bit 4 R-0 R-0 RC4 RS1 0 Bit 3 R-0 R-0 RC5 RS2 0 Bit 2 R-1 R-1 RC6 RS3 0 Bit 1 R-1 R-1 RC7 RM1 RS4 0 Bit 0 R-1 R-1 RC8 RM2 RSPB4 = 1 0
RSPB1 = 0 RSPB2 = 1 RSPB3 = 0
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Framer Register Architecture (continued)
In the CEPT frame format, FRM_SR54 through FRM_SR63 contain the received Sa4 through Sa8 from the last valid CRC-4 double-multiframe. In non-CRC-4 mode, these registers are only updated during a basic frame aligned state. In CRC-4 mode, these registers are only updated during the CRC-4 multiframe alignment state. Table 102. CEPT Sa Receive Stack (FRM_SR54--FRM_SR63) (Y36--Y3F) Register FRM_SR54 FRM_SR55 FRM_SR56 FRM_SR57 FRM_SR58 FRM_SR59 FRM_SR60 FRM_SR61 FRM_SR62 FRM_SR63 Bit 7 Sa4-1 Sa4-17 Sa5-1 Sa5-17 Sa6-1 Sa6-17 Sa7-1 Sa7-17 Sa8-1 Sa8-17 Bit 6 Sa4-3 Sa4-19 Sa5-3 Sa5-19 Sa6-3 Sa6-19 Sa7-3 Sa7-19 Sa8-3 Sa8-19 Bit 5 Sa4-5 Sa4-21 Sa5-5 Sa5-21 Sa6-5 Sa6-21 Sa7-5 Sa7-21 Sa8-5 Sa8-21 Bit 4 Sa4-7 Sa4-23 Sa5-7 Sa5-23 Sa6-7 Sa6-23 Sa7-7 Sa7-23 Sa8-7 Sa8-23 Bit 3 Sa4-9 Sa4-25 Sa5-9 Sa5-25 Sa6-9 Sa6-25 Sa7-9 Sa7-25 Sa8-9 Sa8-25 Bit 2 Sa4-11 Sa4-27 Sa5-11 Sa5-27 Sa6-11 Sa6-27 Sa7-11 Sa7-27 Sa8-11 Sa8-27 Bit 1 Sa4-13 Sa4-29 Sa5-13 Sa5-29 Sa6-13 Sa6-29 Sa7-13 Sa7-29 Sa8-13 Sa8-29 Bit 0 Sa4-15 Sa4-31 Sa5-15 Sa5-31 Sa6-15 Sa6-31 Sa7-15 Sa7-31 Sa8-15 Sa8-31
The receive framer stores the current second of the ANSI Performance Report Message transmitted to the remote end in registers FRM_SR62 and FRM_SR63. The structure of the PRM status registers is shown in Table 103. Table 103. Transmit Framer ANSI Performance Report Message Status Register Structure
Transmit Framer PRM Status Bytes FRM_SR62 FRM_SR63 TSPRM B7 TSPRM B6 TSPRM B5 TSPRM B4 TSPRM B3 TSPRM B2 TSPRM B1 TSPRM B0
G3 FE
LV SE
G4 LB
U1 G1
U2 R
G5 G2
SL Nm
G6 Nl
Received Signaling Registers: DS1 Format Table 104. Received Signaling Registers: DS1 Format (FRM_RSR0--FRM_RSR23) (Y40--Y58) Received Signal Registers DS1 Received Signaling Registers (0--23) Voice Channel with 16-State Signaling Voice Channel with 4-State Signaling Voice Channel with 2-State Signaling Data Channel Bit 7 P
X X X X
Bit 6* G 0 0 1 1
Bit 5 F 0 1 1 0
Bit 4
X X X X X
Bit 3 D D
X X X
Bit 2 C C
X X X
Bit 1 B B B
X X
Bit 0 A A A A
X
* Bit 6 and bit 5 of the DS1 receive signaling registers are copied from bit 6 and bit 5 of the DS1 transmit signaling registers.
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
Receive Signaling Registers: CEPT Format Table 105. Receive Signaling Registers: CEPT Format (FRM_RSR0--FRM_RSR31) (Y40--Y5F) Receive Signal Registers FRM_RSR1--FRM_RSR15 FRM_RSR[17:31] Bit 7 P P Bit 6--5 X X Bit 4* E[1:15] E[17:31] Bit 3 D[1:15] D[17:31] Bit 2 C[1:15] C[17:31] Bit 1 B[1:15] B[17:31] Bit 0 A[1:15] A[17:31]
* In PSCO or PSC1 signaling mode, this bit is undefined.
Framer Parameter/Control Registers
Registers FRM_PR0--FRM_PR70 define the mode configuration of each framer. All are read/write registers. These registers are initially set to a default value upon a hardware reset, which is indicated in the register definition. Interrupt Group Enable Registers (FRM_PR0--FRM_PR7) The bits in this register group enable the status registers FRM_SR0--FRM_SR7 to assert the interrupt pin. The default value of these registers is 00 (hex). FRM_PR0 is the primary interrupt group enable register which enables the event groups in interrupt status register FRM_SR0. A bit set to 1 in this register enables the corresponding bit in the interrupt status register FRM_SR0 to assert the interrupt pin. FRM_PR1--FRM_PR7 are the secondary interrupt enable registers. A bit set to 1 in these registers enables the corresponding bit in the status register to assert the interrupt pin. Table 106. Summary of Interrupt Group Enable Registers (FRM_PR0--FRM_PR7) (Y60--Y67)
Parameter/ Control Register
FRM_PR0
Status Register Enabled
FRM_SR0
Status Register Bit 7
S96SR
Status Register Bit 6
Reserved
Status Register Bit 5
RSSFE
Status Register Bit 4
TSSFE
Status Register Bit 3
Status Register Bit 2
Status Register Bit 1
RAC (read FRM_SR2)
Status Register Bit 0
FAC (read FRM_SR1)
ESE FAE (read (read FRM_SR5, FRM_SR3 FRM_SR6, and and FRM_SR4) FRM_SR7) LFALR RSa6=8 ECE LLBON (CMA) ETUAS NTUAS NROUAS
FRM_PR1 FRM_PR2 FRM_PR3 FRM_PR4 FRM_PR5 FRM_PR6 FRM_PR7
FRM_SR1 FRM_SR2 FRM_SR3
AIS RSa6=F SLIPU
AUXP RSa6=E SLIPO
RTS16AIS RSa6=C LCRCATMX
LBFA RSa6=A REBIT
LTSFA LSFA (LTS0MFA) (LTS16MFA) CREBIT CRCE LLBOFF (BFA) ETSES NTSES NT1OUAS RJYA (RTS16MFA) FBE SSFA ETBES NTBES EROUAS
LFA RFA LFV CFA ETES NTES OUAS
FRM_SR4 FDL_LLBOFF FDL_LLBON FDL_PLBOFF FDL_PLBON (SLCTFSR) (SLCRFSR) (TSaSR) (RSaSR) FRM_SR5 FRM_SR6 FRM_SR7 ETREUAS NTREUAS RQUASI ETRESES NTRESES RPSUEDO ETREBES NTREBES PTRNBER ETREES NTREES DETECT
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Framer Register Architecture (continued)
Primary Interrupt Enable Register (FRM_PR0) The default value of this register is 00 (hex). Table 107. Primary Interrupt Group Enable Register (FRM_PR0) (Y60) Bit 0 1 2 3 4 5 6 7 Symbol SR1IE SR2IE SR34IE SR567IE TSRIE RSRIE -- SLCIE Description Status Register 1 Interrupt Enable Bit. A 1 enables register FRM_SR1 event interrupts. Status Register 2 Interrupt Enable Bit. A 1 enables register FRM_SR2 event interrupts. Status Registers 3 and 4 Interrupt Enable Bit. A 1 enables registers FRM_SR3 and FRM_SR4 event interrupts. Status Registers 5, 6, and 7 Interrupt Enable Bit. A 1 enables registers FRM_SR5, FRM_SR6, and FRM_SR7 event interrupts. Transmit Signaling Ready Interrupt Enable Bit. A 1 enables interrupts when transmit signaling buffers are ready (MOS mode). Receive Signaling Ready Interrupt Enable Bit. A 1 enables interrupts when receive signaling buffers are ready (MOS mode). Reserved. Write to 0. SLC-96 Interrupt Enable Bit. A 1 enables interrupts when SLC-96 receive or transmit stacks are ready.
Secondary Interrupt Enable Registers (FRM_PR1--FRM_PR7) A bit set to 1 in registers FRM_PR1--FRM_PR7 enables the generation of interrupts whenever the corresponding bit in registers FRM_SR1--FRM_SR7 is set. The default value of these registers is 00 (hex). Table 108. Interrupt Enable Register (FRM_PR1) (Y61) Bit 0--7 Symbol SR1B0IE-- SR1B7IE Description Status Register 1 Interrupt Enable. A 1 enables events monitored in register FRM_SR1 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Table 109. Interrupt Enable Register (FRM_PR2) (Y62) Bit 0--7 Symbol SR2B0IE-- SR2B7IE Description Status Register 2 Interrupt Enable. A 1 enables events monitored in register FRM_SR2 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Table 110. Interrupt Enable Register (FRM_PR3) (Y63) Bit 0--7 Symbol SR3B0IE-- SR3B7IE Description Status Register 3 Interrupt Enable. A 1 enables events monitored in register FRM_SR3 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
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Framer Register Architecture (continued)
Table 111. Interrupt Enable Register (FRM_PR4) (Y64) Bit 0--7 Symbol SR4B0IE-- SR4B7IE Description Status Register 4 Interrupt Enable. A 1 enables events monitored in register FRM_SR4 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Table 112. Interrupt Enable Register (FRM_PR5) (Y65) Bit 0--7 Symbol SR5B0IE-- SR5B7IE Description Status Register 5 Interrupt Enable. A 1 enables events monitored in register FRM_SR5 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Table 113. Interrupt Enable Register (FRM_PR6) (Y66) Bit 0--7 Symbol SR6B0IE-- SR6B7IE Description Status Register 6 Interrupt Enable. A 1 enables events monitored in register FRM_SR6 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Table 114. Interrupt Enable Register (FRM_PR7) (Y67) Bit 0--7 Symbol SR7B0IE-- SR7B7IE Description Status Register 7 Interrupt Enable. A 1 enables events monitored in register FRM_SR7 to generate interrupts. Each bit position in this enable register corresponds to the same bit position in the status register.
Framer Mode Option Register (FRM_PR8) The default value of this register is C0 (hex). Table 115. Framer Mode Bits Decoding (FRM_PR8) (Y68) FRM_PR8 Frame Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FMODE FMODE FMODE FMODE FMODE 4 3 2 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0
ESF D4 DDS DDS with FDL SLC-96 Transmit ESF Receive D4 Transmit D4 Receive ESF CEPT with No CRC-4 PCS Mode 0 PCS Mode 1 CEPT with CRC-4 PCS Mode 1 PCS Mode 0
X X X X X X X X X X X
X X X X X X X X X X X
X X X X X X X X X X X
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Framer Register Architecture (continued)
Table 116. Line Code Option Bits Decoding (FRM_PR8) (Y68) Line Code Format B8ZS (T/R) ZCS (T/R) HDB3 (T/R) Single Rail (DEFAULT) AMI (T/R) B8ZS (T), AMI (R) ZCS (T), B8ZS (R) AMI (T), B8ZS (R) Bit 7 LC2 0 0 0 1 0 1 1 1 Bit 6 LC1 0 0 1 1 1 0 0 1 Bit 5 LC0 0 1 0 0 1 0 1 1 Bit 4 X X X X X X X X Bit 3 X X X X X X X X Bit 2 X X X X X X X X Bit 1 X X X X X X X X Bit 0 X X X X X X X X
Framer CRC Control Option Register (FRM_PR9) This register defines the CRC options for the framer. The default setting is 00 (hex). Table 117. CRC Option Bits Decoding (FRM_PR9) (Y69) FRM_PR9 CRC Options Loss of Frame Alignment Due to Excessive CRC Errors (ESF 320, CEPT 915 in a one-second interval) CRC-4 with 100 ms Timer CRC-4 Interworking Search with 400 ms Timer CRC-4 with 990 REB Counter CRC-4 with 990 REB Counter: A Bit = 1 Restart CRC-4 with 990 REB Counter: Sa6-F or Sa6-E Restart XCRC-4/R-NO CRC-4 X-NOCRC-4/RCRC4 CRC Default Mode (No CRC) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 1 1 0 X X X X X 1 X X 0 X X X X 1 X X X 0 X X X 1 1 1 X X 0 X X 1 X X X X X 0 X 1 X X X X X X 0 1 X X X X X X X 0 1 1 1 1 1 1 0 1 0
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Framer Register Architecture (continued)
Alarm Filter Register (FRM_PR10) The bits in this register enable various control options. The default setting is 00 (hex). Table 118. Alarm Filter Register (FRM_PR10) (Y6A) Bit 0 Symbol SSa6M Description Synchronous Sa6 Monitoring. A 0 enables the asynchronous monitoring of the Sa6 codes relative to the receive CRC-4 submultiframe. A 1 enables synchronous monitoring of the Sa6 pattern relative to the receive CRC-4 submultiframe. AIS Detection Mode. A 0 enables the detection of received line AIS as described in ETSI Draft prETS 300 233:1992. A 1 enables the detection of received line AIS as described in ITU Rec. G.775. FER Enable (DS1 Only). A 0 enables only the detection of FT framing bit errors in D4 and SLC-96 modes. A 1 enables the detection of FT and FS framing bit errors. Not FAS Framing Bit Error Control (CEPT Only). A 0 enables the monitoring of errored FAS and errored NOT FAS frames in the framing bit error counter, registers FRM_SR10 and FRM_SR11. A 1 enables the monitoring of only errored FAS frames in this error counter. CNUCLB Enable (CEPT Only). A 0 enables payload loopback with regenerated framing and CRC bits in register FRM_PR24. A 1 enables CEPT nailed-up connect loopback in register FRM_PR24. Reserved. Set to 0. Receive A-Bit Filter (CEPT Only). A 0 makes the occurrence of three consecutive A bit = 1 events assert and three consecutive A bit = 0 events deassert the remote frame alarm, register FRM_SR2 bit 0. A 1 enables the occurrence of a single A-bit event to deassert the remote frame alarm.
1
AISM
2
FEREN NFFE
3
CNUCLBEN
4 5
-- RABF
Bit 6 and bit 7 of FRM_PR10 control the evaluation of the bursty errored parameter as defined in Table 119 below. The EST parameter refers to the errored second threshold defined in register FRM_PR11. The SEST parameter refers to the severely errored second threshold defined in registers FRM_PR12 and FRM_PR13 Table 119. Errored Event Threshold Definition Bit 7, FRM_PR10 ESM1 0 0 Bit 6, FRM_PR10 ESM0 0 1 Errored Second (ES) Definition Bursty Errored Second (BES) Definition Severely Errored Second (SES) Definition SES = 1 when: Errored events > SEST
Other Combinations
Default values in Table 32. ES = 1 when: BES = 0 Errored events > EST Reserved.
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Errored Second Threshold Register (FRM_PR11) This register defines the errored event threshold for an errored second (ES). A one-second interval with errors less than the ES threshold value will not be detected as an errored second. Programming 00 (hex) into this register disables the errored second threshold monitor circuitry if register FRM_PR10 bit 6 = 1 and bit 7 = 0. The default value of this register is 00 (hex). Table 120. Errored Second Threshold Register (FRM_PR11) (Y6B) Register FRM_PR11 Symbol EST7--EST0 ES Threshold Register. Description
Severely Errored Second Threshold Register (FRM_PR12--FRM_PR13) This 16-bit register defines the errored event threshold for a severely errored second (SES). A one-second interval with errors less than the SES threshold value is not a severely errored second. Programming 00 (hex) into these two registers disables the severely errored second threshold monitor circuitry if register FRM_PR10 bit 6 = 1 and bit 7 = 0. The default value of these registers is 00 (hex). Table 121. Severely Errored Second Threshold Registers (FRM_PR12--FRM_PR13) (Y6C--Y6D) Register FRM_PR12 FRM_PR13 Symbol SEST15--SEST8 SEST7--SEST0 SES MSB Threshold Register. SES LSB Threshold Register. Description
ET1 Errored Event Enable Register (FRM_PR14) These bits enable the errored events used to determine errored and severely errored seconds at the local ET interface. ETSLIP ETAIS, ETLMFA, and ETLFA are the SLIP AIS, LMFA, and LFA errored events, respectively, as , , referred to the local ET interface. A 1 in the bit position enables the corresponding errored event. The default value of this register is 00 (hex). Table 122. ET1 Errored Event Enable Register (FRM_PR14) (Y6E) Register FRM_PR14 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 ETSLIP Bit 2 ETAIS Bit 1 ETLMFA Bit 0 ETLFA
ET1 Remote End Errored Event Enable Register* (FRM_PR15) These bits enable the errored events used to determine errored and severely errored seconds at the ET's remote end interface. ETRESa6-F, ETRESa6-E, ETRESa6-8, ETRERFA, ETRESLIP, ETREAIS, ETRELMFA, and ETRELFA are the Sa6-F, Sa6-E, Sa6-8, RFA, SLIP, AIS, LMFA, and LFA errored events, respectively, as referred to the ET remote end interface. A 1 in the bit position enables the corresponding errored event. The default value of this register is 00 (hex). Table 123. ET1 Remote End Errored Event Enable Register (FRM_PR15) (Y6F) Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FRM_PR15 ETRESa6-F ETRESa6-E ETRESa6-8 ETRERFA ETRESLIP ETREAIS ETRELMFA ETRELFA
* One occurrence of any one of these events causes an errored second count increment and a severely errored second count increment.
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
NT1 Errored Event Enable Register* (FRM_PR16) These bits enable the errored events used to determine errored and severely errored seconds at the network termination-1 interface. NTSa6-C, NTSa6-8, NTSLIP NTAIS, NTLMFA, and NTLFA are the Sa6-C, Sa6-8, SLIP AIS, , , LMFA, and LFA errored events, respectively, as referred to the NT1 interface. A 1 in the bit position enables the corresponding errored event. The default value of this register is 00 (hex). Table 124. NT1 Errored Event Enable Register (FRM_PR16) (Y70) Register FRM_PR16 Bit 7 NTSa6-C Bit 6 0 Bit 5 NTSa6-8 Bit 4 0 Bit 3 NTSLIP Bit 2 NTAIS Bit 1 NTLMFA Bit 0 NTLFA
NT1 Remote End Errored Event Enable Register* (FRM_PR17--FRM_PR18) These bits enable the errored events used to determine errored and severely errored seconds at the network termination-1 remote end interface. NTRERFA, NTRESLIP NTREAIS, NTRELMFA, NTRELFA, NTRESa6-C, NTRESa6, F, NTRESa6-E, and NTRESa6-8 are the RFA, SLIP, AIS, LMFA, LFA, Sa6-C, Sa6-F, Sa6-E, and Sa6-8 errored events, respectively, as referred to the NT-1 remote end interface. The default value of this register is 00 (hex). Table 125. NT1 Remote End Errored Event Enable Registers (FRM_PR17--FRM_PR18) (Y71--Y72) Register FRM_PR17 FRM_PR18 Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
NTRERFA NTRESLIP NTREAIS NTRELMFA NTRELFA 0 NTRESa6-C NTRESa6-F NTRESa6-E NTRESa6-8
Automatic AIS to the System and Automatic Loopback Enable Register The default value of this register is 00 (hex). Table 126. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (Y73) Bit 0 1 Symbol ASAIS ASAISTMX Description Automatic System AIS. A 1 transmits AIS to the system whenever the receive framer is in the loss of receive frame alignment (RLFA) state. Automatic System AIS CEPT CRC-4 Timer Expiration. A 1 transmits AIS to the system after the CRC-4 100 ms or 400 ms timer expires. AIS is transmitted for the duration of the loss of CRC-4 multiframe alignment state. Reserved. Set to 0. Transmit System AIS. A 1 transmits AIS to the system. Automatic Line Loopback Enable. A 1 enables the framer section to execute the DS1 line loopback on or off commands without system intervention. Reserved. Set to 0. Automatic FDL Line Loopback Enable. A 1 enables the framer section to execute a line ESF FDL loopback on or off command without system intervention. Automatic FDL Payload Loopback Enable. A 1 enables the framer section to execute a payload ESF FDL loopback on or off command without system intervention.
2 3 4 5 6 7
-- TSAIS ALLBE -- AFDLLBE AFDPLBE
* One occurrence of any one of these events causes an errored second count increment and a severely errored second count increment.
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Automatic AIS to the System and Automatic Loopback Enable Register The default value of this register is 00 (hex). Table 127. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (Y73) Bit 0 1 Symbol ASAIS ASAISTMX Description Automatic System AIS. A 1 transmits AIS to the system whenever the receive framer is in the loss of receive frame alignment (RLFA) state. Automatic System AIS CEPT CRC-4 Timer Expiration. A 1 transmits AIS to the system after the CRC-4 100 ms or 400 ms timer expires. AIS is transmitted for the duration of the loss of CRC-4 multiframe alignment state. Reserved. Set to 0. Transmit System AIS. A 1 transmits AIS to the system. Automatic Line Loopback Enable. A 1 enables the framer section to execute the DS1 line loopback on or off commands without system intervention. Reserved. Set to 0. Automatic FDL Line Loopback Enable. A 1 enables the framer section to execute a line ESF FDL loopback on or off command without system intervention. Automatic FDL Payload Loopback Enable. A 1 enables the framer section to execute a payload ESF FDL loopback on or off command without system intervention.
2 3 4 5 6 7
-- TSAIS ALLBE -- AFDLLBE AFDPLBE
Transmit Test Pattern to the Line Enable Register* This register enables the transmit framer to transmit various test signals to the line interface. The default value of this register is 00 (hex). Note that between enabling the transmission of line loopback on and off codes, this register must be set to 00 (hex) (i.e., to enable transmission of line loopback on code and then off code, write into this register 10 (hex), then 00 (hex), and finally 20 (hex)). Table 128. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (Y74) Bit 0 1 2 3 4 5 6 7 Symbol TUFAIS TUFAUXP TPRS TQRS TLLBON TLLBOFF TLIC TICRC Description Unframed AIS to Line Interface (All Ones Pattern). Unframed AUXP to Line Interface in CEPT Mode (Alternating 010101 Unframed Pattern). Transmit Pseudorandom Signal to Line Interface (215 - 1). Transmit Quasi-Random Signal to Line Interface (220 - 1) (ANSI T1.403). Transmit Framed Payload Line Loopback On Code: 00001. Transmit Framed Payload Line Loopback Off Code: 001. Transmit Line Idle Code of FRM_PR22. When this bit = 1, the line idle code of FRM_PR22 is transmitted to the line in all time slots. Transmit Inverted CRC.
* To transmit test signals using this register, registers FRM_PR69 and FRM_PR70 must be set to 00 (hex).
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Framer Register Architecture (continued)
Framer FDL Control Command Register (FRM_PR21) The default value of this register is 00 (hex). Table 129. Framer FDL Control Command Register (FRM_PR21) (Y75) Bit 0 1 2 3 4 5 6 Symbol -- -- -- -- TFDLLAIS TFDLSAIS TFDLC Description Reserved. Must be set to 0. Reserved. Must be set to 0. Reserved. Must be set to 0. Reserved. Must be set to 0. Transmit Facility Data Link AIS to the Line. A 1 sends AIS in the line side data link. Transmit Facility Data Link AIS to the System. A 1 sends AIS in the system data link side. Transmit FDL Control Bit. A 0 enables the transmission of the FDL bit from the internal FDL-HDLC unit (default). A 1 enables the transmission of the FDL bit from the TFDL input or from the internal transmit stack depending on the state of FRM_PR29 bit 5--bit 7. When the SLC-96 stack transmission is enabled (register FRM_PR26 bit 5--bit 7 = x10 (binary), the FDL bit is sourced from the SLC-96 transmit stack (register FRM_PR31--FRM_PR35). Otherwise, it is sourced from TFDL. Transmit ESF_PRM C/R = 1 (TC/R = 1). A 0 transmits the ESF performance report message with the C/R bit = 0. (See ANSI T1.403-1995 for the PRM structure and content.) A 1 transmits the ESF performance report message with the C/R bit = 1.
7
TC/R=1
Framer Transmit Line Idle Code Register (FRM_PR22) The value programmed in this register is transmitted as the line idle code. The default value is 7F (hex). Table 130. Framer Transmit Line Idle Code Register (FRM_PR22) (Y76) Bit 0--7 Symbol TLIC0--TLIC7 Description Transmit Line Idle Code 0--7. These 8 bits define the idle code transmitted to the line.
Framer System Stuffed Time-Slot Code Register (FRM_PR23) The value programmed in this register is transmitted in the stuffed time slots on the CHI in the DS1 modes. The default value is 7F (hex). Table 131. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (Y77) Bit 0--7 Symbol SSTSC0-- SSTSC7 Description System Stuffed Time-Slot Code 0--7. These 8 bits define the idle code transmitted in the stuffed time slots to the system CHI.
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Framer Register Architecture (continued)
Primary Loopback Mode Control and Time Slot Address (FRM_PR24) This register contains the loopback mode control and the 5-bit address of the line or system time slot to be looped back. The default value is 00 (hex) (no loopback). Table 132. Primary Time-Slot Loopback Address Register (FRM_PR24) (Y78) Bit 0--4 5--7 Symbol TSLBA0-- TSLBA4 LBC0--LBC2 Time-Slot Loopback Address. Loopback Control Bits[2:0]. Description
Table 133. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7--5 LBC2 0 0 0 0 LBC1 0 0 1 1 LBC0 0 1 0 1 Function No Loopback. Line Loopback (LLB). The received line data is looped back to the transmit line data. Board Loopback (BLB). The received system data is looped back to the transmit system data and AIS is sent as the line transmit data. Single Time-Slot System Loopback (STSSLB). System CHI loopback of the time slot selected by bit 4--bit 0. Idle code selected by FRM_PR22 is inserted in the line payload in place of the looped back time slot. Single Time-Slot Line Loopback (STSSLB). Line loopback of time slot selected by bit 4--bit 0. Idle code selected by FRM_PR22 is inserted in the system CHI payload in place of the looped back time slot. CEPT Nailed-Up Broadcast Transmission (CNUBT). Time slot selected by bit 4--bit 0 is transmitted normally and also placed into time slot 0. Payload Line Loopback with Regenerated Framing and CRC Bits. This mode is selected if FRM_PR10 bit 3 = 0. The received channelized-payload data is looped backed to the line. The framing bits are generated within the transmit framer. The regenerated framing information includes the F-bit pattern, the CRC checksum bit, and the system's facility data link bit stream. This loopback mode can be used with the CEPT framing mode. The entire time slot 0 data (FAS and NOT FAS) is regenerated by the transmit framer. The receive framer processes and monitors the incoming line data normally in this loopback mode and transmits the formatted data to the system in the normal format via the CHI. CEPT Nailed-Up Connect Loopback (CNUCLB). The received system time slot selected by this register bit 4--bit 0 is looped back to the system in time slot 0. This mode is selected if FRM_PR10 bit 3 = 1. Payload Line Loopback with Passthrough Framing and CRC Bits. The received channelized/payload data, the CRC bits, and the frame alignment bits are looped back to the line. The system's facility data link bit stream is inserted into the looped back data and transmitted to the line. In ESF, the FDL bits are ignored when calculating the CRC-6 checksum. In CEPT, the FDL bits are included when calculating the CRC-4 checksum, and as such this loopback mode generates CRC-4 errors back at the remote end.
1
0
0
1 1
0 1
1 0
1
1
1
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
Secondary Loopback Control and ID and Address (FRM_PR25) This register allows for a second single-time-slot loopback mode. This loopback is valid if the secondary time slot loopback address is different from the primary loopback address and the device is not in a line, board, or payload loopback, see FRM_PR24. This register contains the secondary loopback mode control and the 5-bit address for the secondary line or system time slot to be looped back to the line or system. The default value is 00 (hex) (no loopback). Table 134. Secondary Time-Slot Loopback Address Register (FRM_PR25) (Y79) Bit 0--4 5--6 7 Symbol STSLBA0--STSLBA4 SLBC0--SLBC1 -- Description Secondary Time-Slot Loopback Address. Secondary Loopback Control Bits[1:0]. Reserved. Write to 0.
Table 135. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6--5 LBC1 0 0 1 1 LBC0 0 1 0 1 Function No Loopback. Secondary Single Time-Slot System Loopback. Secondary Single Time-Slot Line Loopback. Reserved.
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Framer Register Architecture (continued)
Framer Reset and Transparent Mode Control Register (FRM_PR26) The default value of this register is 00 (hex). Table 136. Framer Reset and Transparent Mode Control Register (FRM_PR26) (Y7A) Bits 0 Symbol SWRESET Description
1
2
3
Framer Software Reset. The framer and FDL sections are placed in the reset state for four clock cycles of the frame internal line clock (RFRMCK). The parameter registers are forced to the default values. This bit is self-cleared. SWRESTART Framer Software Restart. The framer and FDL sections are placed in the reset state as long as this bit is set to 1. The framer's parameter registers are not changed from their programmed state. The FDL parameter registers are changed from their programmable state. This bit must be cleared. Framer Reframe. A 0-to-1 transition of this bit forces the receive framer into the loss of FRFRM frame alignment (LFA) state which forces a search of frame alignment. Subsequent reframe commands must have this bit in the 0 state first. Transparent Framing Mode 1. A 1 forces the transmit framer to pass system data TFM1 unmodified to the line and the receive framer to pass line data unmodified to the system. The receive framer is forced not to align to the input receive data. DS1: register FRM_PR43 bit 2--bit 0 must be set to 000. The F bit is located in time slot 0, bit 7. The transmit framer extracts bit 7 of time slot 0 from RCHIDATA and places this bit in the F-bit position of the transmit line data. The receive framer inserts the bit in the F-bit position of the receive line data into time slot 0, bit 7 of the TCHIDATA. CEPT: RCHIDATA time slot 0 is inserted into time slot 0 of the transmit line data. Receive line time slot 0 is inserted into time slot 0 of TCHIDATA. Transparent Framing Mode 2. A 1 forces the transmit framer to pass system data unmodified to the line. The receive framer functions normally as programmed. DS1: register FRM_PR43 bit 2--bit 0 must be set to 000. The F bit is located in time slot 0, bit 7. The transmit framer extracts bit 7 of time slot 0 from RCHIDATA and places this bit in the F-bit position of the transmit line data.
4
TFM2
5
SYSFSM
CEPT: RCHIDATA time slot 0 is inserted into time slot 0 of the transmit line data. System Frame Sync Mask. A 1 masks the system frame synchronization signal in the transmit framer section. Note: The transmit framer must see at least one valid system synchronization pulse to initialize its counts; afterwards, this bit may be set. For those applications that have jitter on the transmit clock signal relative to the system clock signal, enable this bit so that the jitter is isolated from the transmit framer. Reserved. Write to 0.
6--7
--
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
Automatic and Manual Transmission of the Remote Frame Alarm Control Register (FRM_PR27) The default value of this register is 00 (hex). Table 137. Transmission of Remote Frame Alarm and CEPT Automatic Transmission of A Bit = 1 Control Register (FRM_PR27) (Y7B) Bit 0 1 Symbol ARLFA Description
2 3
4 5 6 7
Automatic Remote Frame Alarm on LFA (ARLFA). A 1 transmits the remote frame alarm to the line whenever the receive framer detects loss of frame alignment (RLFA). AAB16LMFA Automatic A Bit on LMFA (CEPT Only). A 1 transmits A = 1 to the line whenever the receive framer detects loss of time slot 16 signaling multiframe alignment (RTS16LMFA). AAB0LMFA Automatic A Bit on LMFA (CEPT Only). A 1 transmits A = 1 to the line whenever the receive framer detects loss of time slot 0 multiframe alignment (RTS0LMFA). Automatic A Bit on CRC-4 Multiframe Reframer Timer Expiration (CEPT Only). A 1 ATMRX transmits A = 1 to the line when the receive framer detects the expiration of either the 100 ms or 400 ms timers due to loss of multiframe alignment. AARSa6_8 Automatic A Bit on RSa6_8 (CEPT Only). A 1 transmits A = 1 to the line whenever the receive framer detects the Sa6 = 1000 pattern. AARSa6_C Automatic A Bit on RSa6_C (CEPT Only). A 1 transmits A = 1 to the line whenever the receive framer detects the Sa6 = 1100 pattern. Transmit D4 Japanese Remote Frame Alarm. A 1 transmits a valid Japanese remote TJRFA frame alarm for the D4 frame format. Transmit Remote Frame Alarm. A 1 transmits a valid remote frame alarm for the correTRFA sponding frame format.
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Framer Register Architecture (continued)
Automatic and Manual Transmission of E Bit = 0 Control Register The default value of this register is 00 (hex). Table 138. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (Y7C) Bit 0 Symbol SIS, Description
1 2 3 4
5
6--7
Si-Bit Source. In CEPT with no CRC-4 mode, a 1 transmits TSiF and TSiNF in the Si bit position to the line in FAS and NOT FAS, respectively. A 0, in non-CRC-4 mode, transmits system Si data to the line transparently*. Transmit One E = 0. In CEPT with CRC-4 mode, a 0 transmits E = TSiF in frame 13 and T1E E = TSiNF in frame 15. A 1 transmits one E bit = 0 for each write access to TSiF = 0 or TSiNF = 0. Transmit Bit 1 in FAS. In CEPT with no CRC-4, this bit can be transmitted to the line in TSiF bit 1 of the FAS. In CRC-4 mode, this bit is used for E-bit data in frame 13. Transmit Bit 1 in NOT FAS. In CEPT with no CRC-4, this bit can be transmitted to the TSiNF line in bit 1 of the NOT FAS. In CRC-4 mode, this bit is used for E-bit data in frame 15. ATERCRCE Automatic Transmit E Bit = 0 for Received CRC-4 Errored Events. A 1 transmits E = 0 to the line whenever the receive framer detects a CRC-4 errored checksum. ATELTS0MFA Automatic Transmit E Bit = 0 for Received Loss of CRC-4 Multiframe Alignment. A 1 transmits E = 0 to the line whenever the receive framer detects a loss of CRC-4 multiframe alignment condition. Automatic Transmit E Bit = 0 on Expiration of CEPT CRC-4 Loss of Multiframe ATERTX Timer. A 1 transmits E = 0 to the line whenever the receive framer detects the expiration of either the 100 ms or 400 ms timer due to the loss of CRC-4 multiframe alignment. These Bits Are Zero. --
* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001XXXXX (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.
Sa4--Sa8 Source Register (FRM_PR29) These bits contain the fixed transmit Sa bits and define the source of the Sa bits. The default value of this register is 00 (hex). Table 139. Sa4--Sa8 Source Register (FRM_PR29) (Y7D) Bit 0--4 5--7 Symbol TSa4--TSa8 SaS5--SaS7 Transmit Sa4--Sa8 Bit. Sa Source Control Bits[2:0]. Description
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Framer Register Architecture (continued)
Table 140. Sa Bits Source Control for Bit 5--Bit 7 in FRM_PR29 SaS7 1 SaS6 0 SaS5 0 Function A single Sa bit, selected in register FRM_PR43, is sourced from either the external transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDLHDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are sourced by this register bit 0--bit 4 if enabled in register FRM_PR30, or transparently from the system interface*. A single Sa bit, selected in register FRM_PR43, is sourced from either the external transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDLHDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are transmitted transparently from the system interface*. A single Sa bit, selected in register FRM_PR43, is sourced from either the external transmit facility data input port TFDL (FRM_PR21 bit 6 = 1) or from the internal FDLHDLC block (FRM_PR21 bit 6 = 0). The remaining Sa bits are sourced from the transmit Sa stack registers (FRM_PR31--FRM_PR40) if enabled in register FRM_PR30, or transparently from the system interface*. SLC-96 Mode. Transmit SLC-96 stack and the SLC-96 interrupts are enabled. The SLC-96 FDL bits are sourced from the transmit SLC-96 stack, registers FRM_PR31-- FRM_PR40. CEPT Mode. Transmit Sa stack and the Sa interrupts are enabled. The Sa bits are sourced from the transmit Sa stack (FRM_PR31--FRM_PR40) if enabled in register FRM_PR30, or transparently from the system interface*. Sa[4:8] bits are transmitted from the system interface transparently through the framer*. Sa[4:8] bits are sourced by bit 0--bit 4 of this register if enabled in register FRM_PR30, or transparently from the system interface*.
1
0
1
1
1
x
0
1
x
0 0
0 0
1 0
* Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system transparently, FRM_PR29 must first be momentarily written to 001XXXXX (binary). Otherwise, the transmit framer will not be able to locate the biframe alignment.
Sa4--Sa8 Control Register (FRM_PR30) In conjunction with FRM_PR29 bit 5--bit 7, these bits define the source of the individual Sa4--Sa8 bits. The default value of this register is 00 (hex). Table 141. Sa4--Sa8 Control Register (FRM_PR30) (Y7E) Bit 0--4 Symbol TESa4--TESa8 Description Transparent Enable Sa4--Sa8 Bit Mask. A 1 enables the transmission of the corresponding Sa bits from the Sa source register (FRM_PR29 bit 0--bit 4) or from the transmit Sa stack. A 0 allows the corresponding Sa bit to be transmitted transparently from the system interface. Reserved. Write to 0. Transmit Double NOT FAS System Time Slot. A 0 enables the transmission of the FAS and NOT FAS on the TCHIDATA interface. A 1 enables the NOT FAS to be transmitted twice on the TCHIDATA interface, and the received time slot 0 from the RCHIDATA is assumed to carry NOT FAS data that is repeated twice.
5--6 7
-- TDNF
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Framer Register Architecture (continued)
Sa Transmit Stack Register (FRM_PR31--FRM_PR40) In CEPT frame format, registers FRM_PR31--FRM_PR40 are used to program the Sa bits in the CEPT multiframe NOT-FAS words. If CRC-4 is enabled, this data is transmitted to the line synchronously to the CRC-4 multiframe. The default value of these registers is 00 (hex). Table 142. Sa Transmit Stack (FRM_PR31--FRM_PR40) (Y7F--Y88) Register FRM_PR31 FRM_PR32 FRM_PR33 FRM_PR34 FRM_PR35 FRM_PR36 FRM_PR37 FRM_PR38 FRM_PR39 FRM_PR40 Bit 7 Sa4-1 Sa4-17 Sa5-1 Sa5-17 Sa6-1 Sa6-17 Sa7-1 Sa7-17 Sa8-1 Sa8-17 Bit 6 Sa4-3 Sa4-19 Sa5-3 Sa5-19 Sa6-3 Sa6-19 Sa7-3 Sa7-19 Sa8-3 Sa8-19 Bit 5 Sa4-5 Sa4-21 Sa5-5 Sa5-21 Sa6-5 Sa6-21 Sa7-5 Sa7-21 Sa8-5 Sa8-21 Bit 4 Sa4-7 Sa4-23 Sa5-7 Sa5-23 Sa6-7 Sa6-23 Sa7-7 Sa7-23 Sa8-7 Sa8-23 Bit 3 Sa4-9 Sa4-25 Sa5-9 Sa5-25 Sa6-9 Sa6-25 Sa7-9 Sa7-25 Sa8-9 Sa8-25 Bit 2 Sa4-11 Sa4-27 Sa5-11 Sa5-27 Sa6-11 Sa6-27 Sa7-11 Sa7-27 Sa8-11 Sa8-27 Bit 1 Sa4-13 Sa4-29 Sa5-13 Sa5-29 Sa6-13 Sa6-29 Sa7-13 Sa7-29 Sa8-13 Sa8-29 Bit 0 Sa4-15 Sa4-31 Sa5-15 Sa5-31 Sa6-15 Sa6-31 Sa7-15 Sa7-31 Sa8-15 Sa8-31
SLC-96 Transmit Stack (FRM_PR31--FRM_PR40)
In SLC-96 frame format, registers FRM_PR31--FRM_PR35 are used to source the transmit facility data link bits in the FS bit positions. The default value of these registers is 00 (hex). Table 143. SLC-96 Transmit Stack (FRM_PR31--FRM_PR40) (Y7F--Y88) Register FRM_PR31 FRM_PR32 FRM_PR33 FRM_PR34 FRM_PR35 FRM_PR36-- FRM_PR40 Bit 7 0 0 XC1 XC9 XM3 0 Bit 6 0 0 XC2 XC10 XA1 0 Bit 5 X-0 X-0 XC3 XC11 XA2 0 Bit 4 Bit 3 Bit 2 Bit 1 X-1 X-1 XC7 XM1 XS4 0 Bit 0 X-1 X-1 XC8 XM2 XSPB4 = 1 0
X-0 X-0 X-1 X-0 X-0 X-1 XC4 XC5 XC6 XSPB1 = 0 XSPB2 = 1 XSPB3 = 0 XS1 XS2 XS3 0 0 0
In SLC-96 frame format, the bits in registers FRM_PR31--FRM_PR35 are transmitted using the format shown in Table 144. Table 144. Transmit SLC-96 FDL Format
FS= 000111000111 XC1 XC2 XC3 XC4 XC5 XC6 XC7 XC8 XC9 XC10 XC11 XSPB1 XSPB2 XSPB3 XM1 XM2 XM3 XA1 XA2 XS1 XS2 XS3 XS4 XSPB4
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register (FRM_PR41) The default value of this register is 00 (hex). Table 145. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm and AIS Control Register (FRM_PR41) (Y89) Bit 0--2 3 4 Symbol Description
5 6 7
TTS16X0--TTS16X2 Transmit Time Slot 16 X0--X2 Bits. The content of these bits are written into CEPT signaling multiframe time slot 16 X bits. X-Bit Source. A 1 enables the TTS16X[2:0] bits to be written into CEPT time slot XS 16 signaling multiframe frame. A 0 transmits the X bits transparently. Automatic Line Transmit Time Slot 16 Remote Multiframe Alarm. A 1 ALTTS16RMFA enables the transmission of CEPT time slot 16 signaling remote multiframe alarm when the receive framer is in the loss of CEPT signaling (RTS16LMFA) state. Transmit Line Time Slot 16 Remote Multiframe Alarm. A 1 enables the transTLTS16RMFA mission of CEPT time slot 16 signaling remote multiframe alarm. Transmit Line Time Slot 16 AIS. A 1 enables the transmission of CEPT time TLTS16AIS slot 16 alarm indication signal. Reserved. Write to 0. --
Framer Exercise Register (FRM_PR42) This register is used for exercising the device in test mode. Setting the framer exercise bits 0--5 as described in Table 146 causes the specified error condition to be generated. In normal operation, it should be set to 00 (hex). The default value of this register is 00 (hex). Table 146. Framer Exercise Register (FRM_PR42) (Y8A) Bit FEX0--FEX5 FEX6 FEX7 0 0 0 1 1 0 1 1 Description Framer Exercise Bits 0--5 (FEX0--FEX5). See Table 147. Pulse wide Interval. 1 s Pulse. 500 ms Pulse. 100 ms Pulse. Reserved.
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Framer Register Architecture (continued)
Table 147. Framer Exercises, FRM_PR42 Bit 5--Bit 0 (Y8A) Exercise Type Facility Status FEX5 FEX4 FEX3 FEX2 0 0 1 0 FEX1 FEX0 0 0 Exercise Line format violation. CRC checksum error. Receive remote frame alarm. Alarm indication signal detection. Loss of frame alignment. Receive remote frame alarm. Time slot 0 1-bit shift. Transmit corrupt CRC. Frame-bit error & loss of frame alignment. Loss of time slot 16 multiframe alignment. Remote frame alarm. CRC bit errors. Frame-bit errors. Frame-bit errors & loss of frame alignment. Loss of time slot 16 multiframe alignment. Frame-bit error & loss of frame alignment. Change of frame alignment. Loss of time slot 16 multiframe alignment. Excessive CRC checksum errors. No test mode activated. Framing Format All ESF or CEPT D4 or ESF All CEPT Japanese D4 CEPT ESF & CEPT All CEPT D4 & DDS ESF & CEPT All All CEPT All ESF, DDS, & CEPT CEPT ESF & CEPT --
0
0
1
0
0
1
0 0
0 0
1 1
0 0
1 1
0 1
0 0
0 0
1 1
1 1
0 0
0 1
0
0
1
1
1
0
0 0
0 0
1 0
1 0
1 0
1 0
158
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
Table 147. Framer Exercises, FRM_PR42 Bit 5--Bit 0 (Y8A) (continued) Exercise Type Performance Status FEX5 FEX4 FEX3 FEX2 0 0 0 0 0 0 0 0 Status Counters 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 FEX1 FEX0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 Exercise Errored second Bursty errored second Severely errored second Severely errored second count Unavailable state Factory test Increment status counters SR6--SR14 Increment status counters SR6--SR14 CRC error counter Errored event counter Errored second counter Severely errored second counter Unavailable second counter Line format violation counter Frame bit error counter Reserved Framing Format All
--
0 0 0 0 0 1 X 0 1 0 1 0 0 1 0 0 1 1 0 1 1 All other combinations
All
--
DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) The default value of this register is 00 (hex). Table 148. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (Y8B) Bit 0--2 Symbol Description
3 4--7
STS0--STS2 In DS1 mode, bit 0--bit 2 program the positions of the stuffed time slots on the CHI. The content of the stuffed time slot can be programmed using register FRM_PR23. Bits 210 000 = SDDDSDDDSDDDSDDDSDDDSDDDSDDDSDDD 001 = DSDDDSDDDSDDDSDDDSDDDSDDDSDDDSDD 010 = DDSDDDSDDDSDDDSDDDSDDDSDDDSDDDSD 011 = DDDSDDDSDDDSDDDSDDDSDDDSDDDSDDDS 100 = DDDDDDDDDDDDDDDDDDDDDDDDSSSSSSSS SaFDL0-- In CEPT mode, bit 0--bit 2 program the Sa-bit source of the facility data link. SaFDL2 Bits 210 000: Sa4 = FDL 001: Sa5 = FDL 010: Sa6 = FDL 011: Sa7 = FDL 100: Sa8 = FDL In both DS1 and CEPT modes, only the bit values shown above may be selected. SLC-96 Signaling Control (DS1 Only). A 1 enables the SLC-96 9-state signaling mode. SSC A 0 enables 16-state signaling in the SLC-96 framing mode. Reserved. Write to 0. -- 159
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Preliminary Data Sheet October 2000
Framer Register Architecture (continued)
Signaling Mode Register (FRM_PR44) This register programs various signaling modes. The default value is 00 (hex). Table 149. Signaling Mode Register (FRM_PR44) (Y8C) Bit 0 Symbol TSIG Description Transparent Signaling. A 0 enables signaling information to be inserted into and extracted from the data stream. The signaling source is either the signaling registers or the system data (in the associated signaling mode). In DS1 modes, the choice of data or voice channels assignment for each channel is a function of the programming of the F and G bits in the transmit signaling registers. A 1 enables data to pass through the device transparently. All channels are treated as data channels. Stomp Mode. A 0 allows the received signaling bits to pass through the receive signaling circuit unmodified. In DS1 robbed-bit signaling modes, a 1 enables the receive signaling circuit to replace (in those time slots programmed for signaling) all signaling bits (in the receive line bit stream) with a 1, after extracting the valid signaling information. In CEPT time slot 16 signaling modes, a 1 enables the received signaling circuit substitute of the signaling combination of ABCD = 0000 to ABCD = 1111. Associated Signaling Mode. A 1 enables the associate signaling mode which configures the CHI to carry both data and its associated signaling information. Enabling this mode must be in conjunction with the programming of the CHI data rate to 4.096 Mbits/s or 8.192 Mbit/s. Each channel consists of 16 bits where 8 bits are data and the remaining 8 bits are signaling information. Receive Signaling Inhibit. A 1 inhibits updating of the receive signaling buffer. Message-Oriented Signaling. DS1: A 1 enables the channel 24 message-oriented signaling mode. TSR-ASM Mode (DS1 Only). In the DS1 mode, setting this bit and FRM_PR44 bit 2 (ASM) to 1 enables the transmit signaling register F and G bits to define the robbed-bit signaling format while the ABCD bit information is extracted from the CHI interface. The F and G bits are copied to the receive signaling block and are used to extract the signaling information from the receive line. Automatic System Transmit Signaling AIS (CEPT Only). A 1 transmits AIS in system time slot 16 during receive loss of time slot 16 signaling multiframe alignment state. Transmit CEPT System Signaling Squelch (CEPT Only). AIS is transmitted in time slot 16 of the transmit system data.
1
STOMP
2
ASM
3 4 5
RSI MOS TSR-ASM
6 7
ASTSAIS TCSS
160
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
CHI Common Control Register (FRM_PR45) These bits define the common attributes of the CHI for TCHIDATA, TCHIDATAB, RCHIDATA, and RCHDATAB. The default value of this register is 00 (hex). Table 150. CHI Common Control Register (FRM_PR45) (Y8D) Bit 0 Symbol HFLF Description High-Frequency/Low-Frequency PLLCK Clock Mode. A 0 enables the low-frequency PLLCK mode for the divide-down circuit in the internal phase-lock loop section (DS1 PLLCK = 1.544 MHz; CEPT PLLCK = 2.048 MHz). The divide-down circuit will produce an 8 kHz signal on DIV-PLLCK, pin G25. A 1 enables the high-frequency PLLCK mode for the divide-down circuit in the internal phase-lock loop section (DS1: PLLCK = 6.176 (4 x 1.544) MHz; CEPT: 8.192 (4 x 2.048) MHz). The divide-down circuit will produce a 32 kHz signal on DIV-PLLCK. Concentration Highway Clock Mode. A 0 enables the CHI clock frequency and CHI data rate to be equal. Function of CMS = 1 is reserved. This control bit affects both the transmit and receive interfaces. Concentration Highway Interface Data Rate Select. Bits CHI Data Rate 23 00 2.048 Mbits/s 01 4.096 Mbits/s 10 8.192 Mbits/s 11 Reserved Concentration Highway Master Mode. A 0 enables external system's frame synchronization signal (CHIFS) to drive the transmit path of the framer's concentration highway interface. A 1 enables the framer's transmit concentration interface to generate a system frame synchronization signal derived from the receive line interface. The framer's system frame synchronization signal is generated on the CHIFS output pin. Applications using the receive line clock as the reference clock signal of the system are recommended to enable this mode and use the CHIFS signal generated by the framer. The receive CHI path is not affected by this mode. Reserved. Write to 0. Highway Enable. A 1 in this bit position enables transmission to the concentration highway. This allows the TFRA08C13 to be fully configured before transmission to the highway. A 0 forces the idle code as defined in register FRM_PR22 to be transmitted to the line in all payload time slots and the transmit CHI pin is forced to a high-impedance state for all CHI transmitted time slots.
1
CMS
2--3
CDRS0-- CDRS1
4
CHIMM
5--6 7
-- HWYEN
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Framer Register Architecture (continued)
CHI Common Control Register (FRM_PR46) This register defines the common attributes of the transmit and receive CHI. The default value is 00 (hex). Table 151. CHI Common Control Register (FRM_PR46) (Y8E) Bit 0--2 Symbol TOFF0-- TOFF2 TFE ROFF0-- ROFF2 RFE Description Transmit CHI Bit Offset. These 3 bits define the bit offset from CHIFS for each transmit time slot. The offset is the number of CHICK clock periods by which the first bit is delayed from TCHIFS. Transmit Frame Clock Edge. A 0 (1) enables the falling (rising) edge of CHICK to latch in the frame synchronization signal, CHIFS. Receive CHI Bit Offset. These 3 bits define the bit offset from CHIFS for each received time slot. The offset is the number of CHICK clock periods by which the first bit is delayed from RCHIFS. Received Frame Clock Edge. A 0 (1) enables the falling (rising) edge of CHICK to latch in the frame synchronization signal, CHIFS.
3 4--6
7
CHI Transmit Control Register (FRM_PR47) The default value of this register is 00 (hex). Table 152. CHI Transmit Control Register (FRM_PR47) (Y8F) Bit 0--5 Symbol TBYOFF0-- TBYOFF5 TCE -- Description Transmit Byte Offset. Combined with FRM_PR65 bit 0 (TBYOFF6), these 6 bits define the byte offset from CHIFS to the beginning of the next transmit CHI frame on TCHIDATA. Transmitter Clock Edge. A 1 (0) enables the rising (falling) edge of CHICK to clock out data on TCHIDATA. Reserved. Write to 0
6 7
CHI Receive Control Register (FRM_PR48) The default value of this register is 00 (hex). Table 153. CHI Receive Control Register (FRM_PR48) (Y90) Bit 0--5 6 7 Symbol RBYOFF0-- RBYOFF5 RCE -- Description Receiver Byte Offset. Combined with FRM_PR66 bit 0 (RBYOFF6), these 6 bits define the byte offset from CHIFS to the beginning of the next receive CHI frame on RCHIDATA. Receiver Clock Edge. A 1 (0) enables the rising (falling) edge of CHICK to latch data on RCHIDATA. Reserved. Write to 0
162
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TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
CHI Transmit Time-Slot Enable Registers (FRM_PR49--FRM_PR52) These four registers define which transmit CHI time slots are enabled. A 1 enables the TCHIDATA or TCHIDATAB time slot. A 0 forces the CHI transmit highway time slot to be 3-stated. The default value of this register is 00 (hex). Table 154. CHI Transmit Time-Slot Enable Registers (FRM_PR49--FRM_PR52) (Y91--Y94) Register FRM_PR49 FRM_PR50 FRM_PR51 FRM_PR52 Bit 7--0 7--0 7--0 7--0 Symbol TTSE31--TTSE24 TTSE23--TTSE16 TTSE15--TTSE8 TTSE7--TTSE0 Description Transmit Time-Slot Enable Bits 31--24. Transmit Time-Slot Enable Bits 23--16. Transmit Time-Slot Enable Bits 15--8. Transmit Time-Slot Enable Bits 7--0.
CHI Receive Time-Slot Enable Registers (FRM_PR53--FRM_PR56) These four registers define which receive CHI time slots are enabled. A 1 enables the RCHIDATA or RCHIDATAB time slots. A 0 disables the time slot and transmits the programmable idle code of register FRM_PR22 to the line in the corresponding time slot. The default value of this register is FF (hex). Table 155. CHI Receive Time-Slot Enable Registers (FRM_PR53--FRM_PR56) (Y95--Y98) Register FRM_PR53 FRM_PR54 FRM_PR55 FRM_PR56 Bit 7--0 7--0 7--0 7--0 Symbol RTSE31--RTSE24 RTSE23--RTSE16 RTSE15--RTSE8 RTSE7--RTSE0 Description Receive Time-Slot Enable Bits 31--24. Receive Time-Slot Enable Bits 23--16. Receive Time-Slot Enable Bits 15--8. Receive Time-Slot Enable Bits 7--0.
CHI Transmit Highway Select Registers (FRM_PR57--FRM_PR60) These four registers define which transmit CHI highway TCHIDATA or TCHIDATAB contains valid data for the active time slot. A 0 enables TCHIDATA, and a 1 enables TCHIDATAB. The default value of this register is 00 (hex). Table 156. CHI Transmit Highway Select Registers (FRM_PR57--FRM_PR60) (Y99--Y9C) Register FRM_PR57 FRM_PR58 FRM_PR59 FRM_PR60 Bit 7--0 7--0 7--0 7--0 Symbol THS31--THS24 THS23--THS16 THS15--THS8 THS7--THS0 Description Transmit Highway Select Bits 31--24. Transmit Highway Select Bits 23--16. Transmit Highway Select Bits 15--8. Transmit Highway Select Bits 7--0.
CHI Receive Highway Select Registers (FRM_PR61--FRM_PR64) These four registers define which receive CHI highway RCHIDATA or RCHIDATAB contains valid data for the active time slot. A 0 enables RCHIDATA and a 1 enables RCHIDATAB. The default value of these registers is 00 (hex). Table 157. CHI Receive Highway Select Registers (FRM_PR61--FRM_PR64) (Y9D--YA0) Register FRM_PR61 FRM_PR62 FRM_PR63 FRM_PR64 Bit 7--0 7--0 7--0 7--0 Symbol RHS31--RHS24 RHS23--RHS16 RHS15--RHS8 RHS7--RHS0 Description Receive Highway Select Bits 31--24. Receive Highway Select Bits 23--16. Receive Highway Select Bits 15--8. Receive Highway Select Bits 7--0. 163
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Preliminary Data Sheet October 2000
Framer Register Architecture (continued)
CHI Transmit Control Register (FRM_PR65) The default value of this register is 00 (hex). Table 158. CHI Transmit Control Register (FRM_PR65) (YA1) Bit 0 Symbol TBYOFF6 Description Transmit CHI 64-Byte Offset. A 1 enables a 64-byte offset from CHIFS to the beginning of the next transmit CHI frame on TCHIDATA. A 0 enables a 0-byte offset (if bit 0--bit 5 of FRM_PR47 = 0). Combing bit 0--bit 5 of FRM_PR47 with this bit allows programming the byte offset from 0--127. Transmit CHI Double Time-Slot Mode. A 1 enables the transmit CHI double time-slot mode. In this mode, the CHI clock runs at twice the rate of TCHIDATA. Reserved. Write to 0.
1 2--7
TCHIDTS --
CHI Receive Control Register (FRM_PR66) The default value of this register is 00 (hex). Table 159. CHI Receive Control Register (FRM_PR66) (YA2)
Bit 0 Symbol RBYOFF6 Description Receive CHI 64-Byte Offset. A 1 enables a 64-byte offset from CHIFS to the beginning of the next receive CHI frame on RCHIDATA. A 0 enables a 0-byte offset (if bit 0-- bit 5 of FRM_PR48 = 0). Combing bit 0--bit 5 of FRM_PR48 with this bit allows programming the byte offset from 0--127. Receive CHI Double Time-Slot Mode. A 1 enables the transmit CHI double time-slot mode. In this mode, the CHI clock runs at twice the rate of RCHIDATA. Reserved. Write to 0.
1 2--7
RCHIDTS --
164
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
Reserved Parameter/Control Registers Registers FRM_PR67 and FRM_PR68, addresses 6A3 and 6A4 or CA3 and CA4, are reserved. Write these registers to 0. Auxiliary Pattern Generator Control Register (FRM_PR69) The following register programs the auxiliary pattern generator in the transmit framer. The default value of this register is 00 (hex). Table 160. Auxiliary Pattern Generator Control Register (FRM_PR69) (YA5)* Bit
0 1 2 3 4--7
Symbol
ITD TPEI GBLKSEL GFRMSEL GPTRN0-- GPTRN3
Description
Invert Transmit Data. Setting this bit to 1 inverts the transmitted pattern. Test Pattern Error Insertion. Toggling this bit from a 0 to a 1 inserts a single bit error in the transmitted test pattern. Generator Block Select. Setting this bit to 1 enables the generation of test patterns in this register. Generator Frame Test Pattern. Setting this bit to 1 results in the generation of an unframed pattern. A 0 results in a framed pattern (T1 and CEPT). Generator Pattern Select. These 4 bits select which random pattern is to be transmitted. Standard Generator Bits Description Polynomial 7654 -- 0000 MARK (all ones) (AIS) -- QRSS (220 - 1 with zero O.151 1+x-17+x-20 0001 suppression) 25 - 1 1+x-3+x-5 -- 0010 6 1+x-1+x-6 63 (2 - 1) -- 0011 511 (29 - 1) 1+x-5+x-9 O.153 0100 1+x-4+x-9 511 (29 - 1) reversed -- 0101 11 1+x-9+x-11 2047 (2 - 1) O.152 0110 2047 (211 - 1) reversed 1+x-2x-11 -- 0111 15 1+x-14+x-15 2 -1 O.151 1000 1+x-3+x-20 220 - 1 O.153 1001 20 2 -1 1+x-17+x-20 CB113/CB114 1010 1+x-18+x-23 223 - 1 O.151 1011 -- 1:1 (alternating) -- 1100
* To generate test pattern signals using this register, register FRM_PR20 must be set to 00 (hex).
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Framer Register Architecture (continued)
Pattern Detector Control Register (FRM_PR70) The following register programs the pattern detector in the receive framer. The default value of this register is 00 (hex). This register must be set to 00 (hex) before a pattern is selected or changed. This register must be set to 00 (hex) to clean register FRM_SR7. Once a selected pattern is detected, the detector remains locked to that alignment and all differences from the expected are reported an bit errors. Pattern-realignment can only occur following a reset of this register, setting it to 00 (hex). Table 161. Pattern Detector Control Register (FRM_PR70) (YA6)* Bit 0 1 2 3
4--7
Symbol IRD -- DBLKSEL DUFTP
DPTRN0-- DPTRN3
Description Invert Receive Data. Setting this bit to 1 enables the pattern detector to detect the inverse of the selected pattern. Reserved. Write to 0. Detector Block Select. Setting this bit to 1 enables the detection of test patterns in this register. Detect Unframed Test Pattern. Setting this bit to 1 results in the search for an unframed pattern. A 0 results in a search for a framed pattern (T1 and CEPT). Detector Pattern Select. These 4 bits select which random pattern is to be Detected. Standard Generator Bits Description Polynomial 7654 -- -- 0000 MARK (all ones) (AIS) O.151 QRSS (220 - 1 with zero 1+x-17+x-20 0001 suppression) -- 25 - 1 1+x-3+x-5 0010 6 -- 63 (2 - 1) 1+x-1+x-6 0011 O.153 511 (29 - 1) 1+x-5+x-9 0100 -- 1+x-4+x-9 511 (29 - 1) reversed 0101 11 O.152 2047 (2 - 1) 1+x-9+x-11 0110 -- 2047 (211 - 1) reversed 1+x-2x-11 0111 15 O.151 1+x-14+x-15 2 -1 1000 O.153 220 - 1 1+x-3+x-20 1001 20 CB113/CB114 1+x-17+x-20 2 -1 1010 1+x-18+x-23 O.151 223 - 1 1011 1:1 (alternating) -- -- 1100
* To generate/detect test pattern signals using this register, register FRM_PR20 must be set to 00 (hex).
166
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Framer Register Architecture (continued)
Transmit Signaling Registers: DS1 Format (FRM_TSR0--FRM_TSR23) These registers program the transmit signaling registers for the DS1 and CEPT mode. The default value of these registers is 00 (hex). Table 162. Transmit Signaling Registers: DS1 Format (FRM_TSR0--FRM_TSR23) (YE0--YF7) Transmit Signal Registers DS1 Transmit Signaling Registers (0--23) ESF Format: Voice Channel with 16-State Signaling SLC-96: 9-State Signaling (depending on the setting in register FRM_PR43) Voice Channel with 4-State Signaling Voice Channel with 2-State Signaling Data Channel (no signaling) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P X G 0 F 0 X X D D C C B B A A
X X X
0 1 1
1 1 0
X X X
X X X
X X X
B A X
A A X
Transmit Signaling Registers: CEPT Format (FRM_TSR0--FRM_TSR31) Table 163. Transmit Signaling Registers: CEPT Format (FRM_TSR0--FRM_TSR31) (YE0--YFF) Transmit Signal Registers FRM_TSR1--FRM_TSR15 FRM_TSR17--FRM_TSR31 Bit 7 P P Bit 6--5 X X Bit 4* E[1:15] E[17:31] Bit 3 D[1:15] D[17:31] Bit 2 C[1:15] C[17:31] Bit 1 B[1:15] B[17:31] Bit 0 A[1:15] A[17:31]
* In PCS0 or PCS1 signaling mode, this bit is undefined.
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FDL Register Architecture
REGBANK9--REGBANK12 contain the status and programmable control registers for the facility data link channels FDL1--FDL8, respectively. The base address for REGBANK9 is A00 (hex), REGBANK10 is B00 (hex), REGBANK11 is C00 (hex), and for REGBANK12 is D00 (hex). Within these register banks, the bit map is identical for FDL1--FDL8. The register bank architecture for FDL1--FDL8 is shown in Table 164. The register bank consists of 8-bit registers classified as either (programmable) parameter registers or status registers. Default values are shown in parentheses. Table 164. FDL Register Set ((A00--A0E); (A20--A2E); (B00--B0E); (B20--B2E) (C00--C0E); (C20--C2E); (D00--D0E); (D20--D2E))
FDL Register Register Address* (hexadecimal) FDL 1 FDL 3 FDL 5 FDL 7 FDL_PR0 FDL_PR1 FDL_PR2 FDL_PR3 FDL_PR4 FDL_PR5 FDL_PR6 FDL_PR8 FDL_PR9 FDL_PR10 FDL_SR0 FDL_SR1 FDL_SR2 FDL_SR3 FDL_SR4 Y00 Y01 Y02 Y03 Y04 Y05 Y06 Y08 Y09 Y0A Y0B Y0C Y0D Y0E Y07 FDL 2 FDL 4 FDL 6 FDL 8 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y28 Y29 Y2A Y2B Y2C Y2D Y2E Y27 FRANSIT3 (1) FTPRM (0) FTBCRC (0) FTFC (0) FTD7 (0) FTIC7 (0) FRANSIE (0) FRMC7 (0) Reserved (0) FTANSI (0) FRANSI FTED FREOF 0 FRD7 FRANSIT2 (0) FRPF (0) FRIIE (0) FTABT (0) FTD6 (0) FTIC6 (0) AFDLBPM (0) FRMC6 (0) FTM (0) Reserved (0) FRIDL FTQS6 FRQS6 0 FRD6 FRANSIT1 (1) FTR (0) FROVIE (0) FTIL5 (0) FTD5 (0) FTIC5 (0) FRIL5 (0) FRMC5 (0) FMATCH (0) FTANSI5 (0) FROVERUN FTQS5 FRQS5 X5 FRD5 FRANSIT0 Reserved (0) (0) FRR (0) FREOFIE (0) FTIL4 (0) FTD4 (0) FTIC4 (0) FRIL4 (0) FRMC4 (0) FALOCT (0) FTANSI4 (0) FREOF FTQS4 FRQS4 X4 FRD4 FTE (0) FRFIE (0) FTIL3 (0) FTD3 (0) FTIC3 (0) FRIL3 (0) FRMC3 (0) FMSTAT (0) FTANSI3 (0) FRF FTQS3 FRQS3 X3 FRD3 Reserved (0) FRE (0) FTUNDIE (0) FTIL2 (0) FTD2 (0) FTIC2 (0) FRIL2 (0) FRMC2 (0) FOCTOF2 (0) FTANSI2 (0) FTUNDABT FTQS2 FRQS2 X2 FRD2 FLAGS (0) FLLB (0) FTEIE (0) FTIL1 (0) FTD1 (0) FTIC1 (0) FRIL1 (0) FRMC1 (0) FDINT (0) FRLB (0) FTDIE (0) FTIL0 (0) FTD0 (0) FTIC0 (0) FRIL0 (0) FRMC0 (0) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
FOCTOF1 FOCTOF0 (0) (0) FTANSI1 (0) FTEM FTQS1 FRQS1 X1 FRD1 FTANSI0 (0) FTDONE FTQS0 FRQS0 X0 FRD0
* For FDL 1 and FDL 2, Y = A; for FDL 3 and FDL 4, Y = B; for FDL 5 and FDL 6, Y = C; for FDL 7 and FDL 8, Y = D.
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
FDL Parameter/Control Registers ((A00--A0E); (A20--A2E); (B00--B0E); (B20--B2E) (C00--C0E); (C20--C2E); (D00--D0E); (D20--D2E))
These registers define the mode configuration of each framer unit. These registers are initially set to a default value upon a hardware reset. These registers are all read/write registers. Default states of all bits in this register group are also indicated in the parameter/control register map. Table 165. FDL Configuration Control Register (FDL_PR0) (A00; A20; B00; B20; C00; C20; D00; D20) Bit 0 Symbol FDINT Description
1
2--3 4--7
Dynamic Interrupt. FDINT = 0 causes multiple occurrences of the same event to generate a single interrupt before the interrupt bit is cleared by reading register FDL_SR0. FDINT = 1 causes multiple interrupts to be generated. This bit should normally be set to 0. Flags. FLAGS = 0 forces the transmission of the idle pattern (11111111) in the absence FLAGS of transmit FDL information. FLAGS = 1 forces the transmission of the fla g pattern (01111110) in the absence of transmit FDL information. This bit resets to 0. Reserved. Write to 0. -- FRANSIT0-- Receive ANSI Bit Code Threshold. These bits define the number of ESF ANSI bit FRANSIT3 codes needed for indicating a valid code. The default is ten (1010 (binary))*.
* The FRANSIT bits (FDL_PR0 bits 4--7) must be changed only following an FDL reset or when the FDL is idle.
Table 166. FDL Control Register (FDL_PR1) (A01; A21; B01; B21; C01; C21; D01; D21) Bit 0 1 Symbol FRLB FLLB Description Remote Loopback. FRLB = 1 loops the received facility data back to the transmit facility data interface. This bit resets to 0. Local Loopback. FLLB = 1 loops transmit facility data back to the receive facility data link interface. The receive facility data link information from the framer interface is ignored. This bit resets to 0. FDL Receiver Enable. FRE = 1 activates the FDL receiver. FRE = 0 forces the FDL receiver into an inactive state. This bit resets to 0. FDL Transmitter Enable. FTE = 1 activates the FDL transmitter. FTE = 0 forces the FDL transmitter into an inactive state. This bit resets to 0. FDL Receiver Reset. FRR = 1 generates an internal pulse that resets the FDL receiver. The FDL receiver FIFO and related circuitry are cleared. The FREOF, FRF, FRIDL, and OVERRUN interrupts are cleared. This bit resets to 0. FDL Transmitter Reset. FTR = 1 generates an internal pulse that resets the FDL transmitter. The FDL transmit FIFO and related circuitry are cleared. The FTUNDABT bit is cleared, and the FTEM interrupt is set; the FTDONE bit is forced to 0 in the HDLC mode and forced to 1 in the transparent mode. This bit resets to 0. FDL Receive PRM Frames. FRPF = 1 allows the receive FDL unit to write the entire receive performance report message including the frame header and CRC data into the receive FDL FIFO. This bit resets to 0. Transmit PRM Enable. When this bit is set, the receive framer will write into the transmit FDL FIFO its performance report message data. The current second of this data is stored in the receive framer's status registers. The receive framer's PRM is transmitted once per second. The PRM is followed by either idles or flags transmitted after the PRM. When this bit is 0, the transmit FDL expects data from the microprocessor interface.
2 3 4
FRE FTE FRR
5
FTR
6
FRPF
7
FTPRM
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FDL Parameter/Control Registers ((A00--A0E); (A20--A2E); (B00--B0E); (B20--B2E) (C00--C0E); (C20--C2E); (D00--D0E); (D20--D2E)) (continued)
Table 167. FDL Interrupt Mask Control Register (FDL_PR2) (A02; A22; B02; B22; C02; C22; D02; D22) Bit 0 Symbol FTDIE Description FDL Transmit-Done Interrupt Enable. When this interrupt enable bit is set, an INTERRUPT pin transition is generated after the last bit of the closing flag or abort sequence is sent. In the transparent mode (register FDL_PR9 bit 6 = 1), an INTERRUPT pin transition is generated when the transmit FIFO is completely empty. FTDIE is cleared upon reset. FDL Transmitter-Empty Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when the transmit FIFO has reached the programmed empty level (see register FDL_PR3). FTEIE is cleared upon reset. FDL Transmit Underrun Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when the transmit FIFO has underrun. FTUNDIE is cleared upon reset and is not used in the transparent mode. FDL Receiver-Full Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when the receive FIFO has reached the programmed full level (see register FDL_PR6). FRFIE is cleared upon reset. FDL Receive End-of-Frame Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when an end-of-frame is detected by the FDL receiver. FREOFIE is cleared upon reset and is not used in the transparent mode. FDL Receiver Overrun Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when the receive FIFO overruns. FROVIE is cleared upon reset. FDL Receiver Idle-Interrupt Enable. When this interrupt-enable bit is set, an INTERRUPT pin transition is generated when the receiver enters the idle state. FRIIR is cleared upon reset and is not used in the transparent mode. FDL Transmit Bad CRC. Setting this bit to 1 forces bad CRCs to be sent on all transmitted frames (for test purposes) until the FTBCRC bit is cleared to 0.
1
FTEIE
2
FTUNDIE
3
FRFIE
4
FREOFIE
5
FROVIE
6
FRIIE
7
FTBCRC
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FDL Parameter/Control Registers ((A00--A0E); (A20--A2E); (B00--B0E); (B20--B2E) (C00--C0E); (C20--C2E); (D00--D0E); (D20--D2E)) (continued)
Table 168. FDL Transmitter Configuration Control Register (FDL_PR3) (A03; A23; B03; B23; C03; C23; D03; D23) Bit 0--5 Symbol Description
61
71
FTIL0--FTIL5 FDL Transmitter Interrupt Level. These bits specify the minimum number of empty positions in the transmit FIFO which triggers a transmitter-empty (FTEM) interrupt. Encoding is in binary; bit 0 is the least significant bit. A code of 001010 will generate an interrupt when the transmit FIFO has ten or more empty locations. The code 000000 generates an interrupt when the transmit FIFO is empty. The number of empty transmit FIFO locations is obtained by reading the transmit FDL status register FDL_SR1. FDL Transmitter Abort. FTABT = 1 forces the transmit FDL unit to abort the frame at the FTABT last user data byte waiting for transmission. When the transmitter reads the byte tagged with FTABT, the abort sequence (01111111) is transmitted in its place. A full byte is guaranteed to be transmitted. Once set for a specific data byte, the internal FTABT status cannot be cleared by writing to this bit. Clearing this bit has no effect on a previously written FTABT. The last value written to FTABT is available for reading. FDL Transmitter Frame Complete. FTFC = 1 forces the transmit FDL unit to terminate FTFC the frame normally after the last user data byte is written to the transmit FIFO. The CRC sequence and a closing flag are appended. FTFC should be set to 1 within 1 ms of writing the last byte of the frame in the transmit FIFO. When the transmit FIFO is empty, writing two data bytes to the FIFO before setting FTCF provides a minimum of 1 ms to write FTFC = 1. Once set for a specific data byte, the internal FTFC status bit cannot be cleared by writing to this bit. Clearing this bit has no effect on a previously written FTFC. The last value written to FTFC is available for reading.
1. Do not set FTABT = 1 and FTFC = 1 at the same time.
Table 169. FDL Transmitter FIFO Register (FDL_PR4) (A04; A24; B04; B24; C04; C24; D04; D24) Bit 0--7 Symbol Description
FTD0--FTD7 FDL Transmit Data. The user data to be transmitted via the FDL block are loaded through this register.
Table 170. FDL Transmitter Idle Character Register (FDL_PR5) (A05; A25; B05; B25; C05; C25; D05; D25) Bit 0--7 Symbol Description
FTIC0--FTIC7 FDL Transmitter Idle Character. This character is used only in transparent mode (register FDL_PR9 bit 6 = 1). When the pattern match bit (register FDL_PR9 bit 5) is set to 1, the FDL transmit unit sends this character whenever the transmit FIFO is empty. The default is to send the ones idle character, but any character can be programmed by the user.
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FDL Parameter/Control Registers ((A00--A0E); (A20--A2E); (B00--B0E); (B20--B2E) (C00--C0E); (C20--C2E); (D00--D0E); (D20--D2E)) (continued)
Table 171. FDL Receiver Interrupt Level Control Register (FDL_PR6) (A06; A26; B06; B26; C06; C26; D06; D26) Bit 0--5 Symbol Description
6 7
FRIL0--FRIL5 FDL Receive Interrupt Level. Bit 0--bit 5 define receiver FIFO full threshold value that will generate the corresponding FRF interrupt. FRIL = 000000 forces the receive FDL FIFO to generate an interrupt when the receive FIFO is completely full. FRIL = 001111 will force the receive FDL FIFO to generate an interrupt when the receive FIFO contains 15 or more bytes. Reserved. Write to 0. -- FDL Receiver ANSI Bit Codes Interrupt Enable. If this bit is set to 1, an interrupt pin FRANSIE condition is generated whenever a valid ANSI code is received.
Table 172. FDL Register FDL_PR7 Bit 0--7 Symbol -- Reserved. Description
Table 173. FDL Receiver Match Character Register (FDL_PR8) (A08; A28; B08; B28; C08; C28; D08; D28) Bit 0--7 Symbol FRMC0-- FRMC7 Description Receiver FDL Match Character. This character is used only in transparent mode (register FDL_PR9 bit 6 = 1). When the pattern match bit (register FDL_PR9 bit 5) is set to 1, the receive FDL unit searches the incoming bit stream for the receiver match character. Data is loaded into the receive FIFO only after this character has been identified. The byte identified as matching the receiver match character is the first byte loaded into the receive FIFO. The default is to search for a flag, but any character can be programmed by the user. The search for the receiver match character can be in a sliding window fashion (register FDL_PR9 bit 4 = 0) or only on byte boundaries (register FDL_PR9 bit 4 = 1).
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FDL Parameter/Control Registers ((A00--A0E); (A20--A2E); (B00--B0E); (B20--B2E) (C00--C0E); (C20--C2E); (D00--D0E); (D20--D2E)) (continued)
Table 174. FDL Transparent Control Register (FDL_PR9) (A09; A29; B09; B29; C09; C29; D09; D29) Bit 0--2 Symbol FOCTOF0-- FOCTOF2 FMSTAT Description FDL Octet Offset (Read Only). These bits record the offset relative to the octet boundary when the receive character was matched. The FOCTOF bits are valid when register FDL_PR9 bit 3 (FMSTAT) is set to 1. A value of 111 (binary) indicates byte alignment. Match Status (Read Only). When this bit is set to 1 by the receive FDL unit, the receiver match character has been recognized. The octet offset status bits (FDL_PR9 bit[2:0]) indicates the offset relative to the octet boundary* at which the receive character was matched. If no match is being performed (register FDL_PR9 bit 5 = 0), the FMSTAT bit is set to 1 automatically when the first byte is received, and the octet offset status bits (register FDL_PR9 bit 0--bit 2) are set to 111 (binary). Frame-Sync Align. When this bit is set to 1, the receive FDL unit searches for the receive match character (FDL-PR8) only on an octet boundary. When this bit is 0, the receive FDL unit searches for the receive match character in a sliding window fashion. Pattern Match. FMATCH affects both the transmitter and receiver. When this bit is set to 1, the FDL does not load data into the receive FIFO until the receive match character programmed in register FDL_PR8 has been detected. The search for the receive match character is in a sliding window fashion if register FDL_PR9 bit 4 is 0, or only on octet boundaries if register FDL_PR9 bit 4 is set to 1. When this bit is 0, the receive FDL unit loads the matched byte and all subsequent data directly into the receive FIFO. On the transmit side, when this bit is set to 1 the transmitter sends the transmit idle character programmed into register FDL_PR5 when the transmit FIFO has no user data. The default idle is to transmit the HDLC ones idle character (FF hexadecimal); however, any value can be used by programming the transmit idle character register FDL_PR5. If this bit is 0, the transmitter sends ones idle characters when the transmit FIFO is empty. FDL Transparent Mode. When this bit is set to 1, the FDL unit performs no HDLC processing on incoming or outgoing data. Reserved. Write to 0.
3
4
FALOCT
5
FMATCH
6 7
FTM --
* The octet boundary is relative the first receive clock edge after the receiver has been enabled (ENR, FDL_PR1 bit 2 = 1).
Table 175. FDL Transmit ANSI ESF Bit Codes (FDL_PR10) (A0A; A2A; B0A; B2A; C0A; C2A; D0A; D2A) Bit 0--5 6 7 Symbol FTANSI0-- FTANSI5 -- FTANSI Description FDL ESF Bit-Oriented Message Data. The transmit ESF FDL bit messages are in the form 111111110X0X1X2X3X4X50, where the order of transmission is from left to right. Reserved. Write to 0. Transmit ANSI Bit Codes. When this bit is set to 1, the FDL unit will continuously transmit the ANSI code defined using register FDL_PR10 bit 0--bit 5 as the ESF bit code messages. This bit must stay high long enough to ensure the ANSI code is sent at least 10 times.
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FDL Parameter/Control Registers ((A00--A0E); (A20--A2E); (B00--B0E); (B20--B2E) (C00--C0E); (C20--C2E); (D00--D0E); (D20--D2E)) (continued)
Table 176. FDL Interrupt Status Register (Clear on Read) (FDL_SR0) (A0B; A2B; B0B; B2B; C0B; C2B; D0B; D2B) Bit 0 Symbol FTDONE Description Transmit Done. This status bit is set to 1 when transmission of the current FDL frame has been completed, either after the last bit of the closing flag or after the last bit of an abort sequence. In the transparent mode (FDL_PR9 bit 6 = 1), this status bit is set when the transmit FIFO is completely empty. A hardware interrupt is generated only if the corresponding interrupt-enable bit (FDL_PR2 bit 0) is set. This status bit is cleared to 0 by a read of this register. Transmitter Empty. If this bit is set to 1, the FDL transmit FIFO is at or below the programmed depth. A hardware interrupt is generated only if the corresponding interruptenable bit (FDL_PR2 bit 1) is set. If DINT (FDL_PR0 bit 0) is 0, this status bit is cleared by a read of this register. If FDINT (FDL_PR0 bit 0) is set to 1, this bit actually represents the dynamic transmit empty condition, and is cleared to 0 only when the transmit FIFO is loaded above the programmed empty level. FDL Transmit Underrun Abort. A 1 indicates that an abort was transmitted because of a transmit FIFO underrun. A hardware interrupt is generated only if the corresponding interrupt-enable bit (FDL_PR2 bit 2) is set. This status bit is cleared to 0 by a read of this register. This bit must be cleared to 0 before further transmission of data is allowed. This interrupt is not generated in the transparent mode. FDL Receiver Full. This bit is set to 1 when the receive FIFO is at or above the programmed full level (FDL_PR6). A hardware interrupt is generated if the corresponding interrupt-enable bit (FDL_PR2 bit 3) is set. If FDINT (FDL_PR0 bit 0) is 0, this status bit is cleared to 0 by a read of this register. If FDINT (FDL_PR0 bit 0) is set to 1, then this bit is cleared only when the receive FIFO is read (or emptied) below the programmed full level*. FDL Receive End of Frame. This bit is set to 1 when the receiver has finished receiving a frame. It becomes 1 upon reception of the last bit of the closing flag of a frame or the last bit of an abort sequence. A hardware interrupt is generated only if the corresponding interrupt-enable bit (FDL_PR2 bit 4) is set. This status bit is cleared to 0 by a read of this register. This interrupt is not generated in the transparent mode. FDL Receiver Overrun. This bit is set to 1 when the receive FIFO has overrun its capacity. A hardware interrupt is generated only if the corresponding interrupt-enable bit (FDL_PR2 bit 5) is set. This status bit is cleared to 0 by a read of this register*. FDL Receiver Idle. This bit is set to 1 when the FDL receiver is idle (i.e., 15 or more consecutive ones have been received). A hardware interrupt is generated only if the corresponding interrupt-enable bit (FDL_PR2 bit 6) is set. This status bit is cleared to 0 by a read of this register. This interrupt is not generated in the transparent mode. FDL Receive ANSI Bit Codes. This bit is set to 1 when the FDL receiver recognizes a valid T1.403 ESF FDL bit code. The receive ANSI bit code is stored in register FDL_SR3. An interrupt is generated only if the corresponding interrupt enable of register FDL_PR6 bit 7 = 1. This status bit is cleared to 0 by a read this register.
1
FTEM
2
FTUNDABT
3
FRF
4
FREOF
5
FROVERUN
6
FRIDL
7
FRANSI
* If an FDL receive FIFO overrun occurs, as indicated by register FDL_SR0 bit 5 (FROVERUN) = 1, the FDL must be reset to restore proper operation of the FIFO. Following an FDL receive FIFO overrun, data extracted prior to the required reset may be corrupted.
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FDL Parameter/Control Registers ((A00--A0E); (A20--A2E); (B00--B0E); (B20--B2E) (C00--C0E); (C20--C2E); (D00--D0E); (D20--D2E)) (continued)
Table 177. FDL Transmitter Status Register (FDL_SR1) (A0C; A2C; B0C; B2C; C0C; C2C; D0C; D2C) Bit 0--6 7 Symbol FTQS0-- FTQS6 FTED Description FDL Transmit Queue Status. Bit 0--bit 6 indicate how many bytes can be added to the transmit FIFO*. The bits are encoded in binary where bit 0 is the least significant bit. FDL Transmitter Empty Dynamic. FTED = 1 indicates that the number of empty locations available in the transmit FIFO is greater than or equal to the value programmed in the FTIL bits (FDL_PR3).
* The count of FDL_SR1 bits 0--6 includes SF byte.
Table 178. FDL Receiver Status Register (FDL_SR2) (A0D; A2D; B0D; B2D; C0D; C2D; D0D; D2D) Bit 0--6 Symbol FRQS0-- FRQS6 FEOF Description FDL Receive Queue Status. Bit 0--bit 6 indicate how many bytes are in the receive FIFO, including the first status of Frame (SF) byte. The bits are encoded in binary where bit 0 is the least significant bit*. FDL End of Frame. When FEOF = 1, the receive queue status indicates the number of bytes up to and including the first SF byte.
7
* Immediately following an FDL reset, the value in bit 0--bit 6 of this status register is 0. After the initial read of the FDL receive FIFO, the value in bit 0--bit 6 of this status register is the number of bytes, including SF byte, that may be read from the FIFO.
Received FDL ANSI Bit Codes Status Register (FDL_SR3) The 6-bit code extracted from the ANSI code 111111110X0X1X2X3X4X50 is stored in this register. Table 179. Receive ANSI FDL Status Register (FDL_SR3) (A0E; A2E; B0E; B2E; C0E; C2E; D0E; D2E) B7 0 B6 0 B5 X5 B4 X4 B3 X3 B2 X2 B1 X1 B0 X0
Receive FDL FIFO Register (FDL_SR4) This FIFO stores the received FDL data. Only valid FIFO bytes indicated in register FDL_SR2 may be read. Reading nonvalid FIFO locations or reading the FIFO when it is empty will corrupt the FIFO pointer and will require an FDL reset to restore proper FDL operation. Table 180. FDL Receiver FIFO Register (FDL_SR4) (A07; A27; B07; B27; C07; C27; D07; D27) Bit 0--7 Symbol Description
FRD0--FRD7 FDL Receive Data. The user data received via the FDL block are read through this register.
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Register Maps
Global Registers
Table 181. Global Register Set
Register Clear on Read (COR) Read (R) Write (W) COR R/W R/W R/W R/W R R R R/W R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hex)
GREG0 GREG1 GREG2 GREG3 GREG4 GREG5 GREG6 GREG7 GREG8 GREG9
FRMR8_INT FRMR7_INT FRMR6_INT FRMR5_INT FRMR4_INT FRMR3_INT FRMR2_INT FRMR1_INT (0) (0) (0) (0) (0) (0) (0) (0) FRMR8IE (0) FDL8_INT (0) FDL8IE (0) Reserved (0) 1 0 0 Reserved (0) EIPLLCK8 (0) FRMR7IE (0) FDL7_INT (0) FDL7IE (0) IPC (0) 1 0 0 DIVMUX0 (0) EIPLLCK7 (0) FRMR6IE (0) FDL6_INT (0) FDL6IE (0) Reserved (0) 1 0 0 DIVMUX1 (0) EIPLLCK6 (0) FRMR5IE (0) FDL5_INT (0) FDL5IE (0) ITSC (0) 1 0 0 DIVMUX2 (0) EIPLLCK5 (0) FRMR4IE (0) FDL4_INT (0) FDL4E (0) Reserved (0) 1 0 0 Reserved (0) EIPLLCK4 (0) FRMR3IE (0) FDL3_INT (0) FDL3IE (0) SECCTRL0 (0) 0 0 0 LOMUX0 (0) EIPLLCK3 (0) FRMR2IE (0) FDL2_INT (0) FDL2IE (0) SECCTRL1 (0) 0 1 0 LOMUX1 (0) EIPLLCK2 (0) FRMR1IE (0) FDL1_INT (0) FDL1IE (0) SECCTRL2 (0) 0 1 1 LOMUX2 (0) EIPLLCK1 (0)
000 001 002 003 004 005 006 007 008 009
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Register Maps (continued)
Framer Parameter/Control Registers (Read-Write)
The address of the registers is shown with the most significant digit, designated by Y, which is used to identify each framer (for framer 1--framer 8, Y = 2--9, respectively). Table 182. Framer Unit Status Register Map
Framer Status Clear on Read (COR) Read (R) Write (W) COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hex) Framer 1--8 S96SR AIS RSa6=F SLIPU FDL-LLBOFF TSaSR ETREUAS NTREUAS RQUASI BPV15 BPV7 FE15 FE7 CEC15 CEC7 REC15 REC7 CNT15 CNT7 ENT15 ENT7 ETES15 ETES7 ETBES15 ETBES7 ETSES15 ETSES7 ETUS15 ETUS7 ETREES15 ETREES7 ETREBES15 ETREBES7 ETRESES15 ETRESES7 ETREUS15 ETREUS7 0 AUXP RSa6=E SLIPO FDL-LLBON RSaSR ETRESES NTRESES RPSEUDO BPV14 BPV6 FE14 FE6 CEC14 CEC6 REC14 REC6 CNT14 CNT6 ENT14 ENT6 ETES14 ETES6 ETBES14 ETBES6 ETSES14 ETSES6 ETUS14 ETUS6 ETREES14 ETREES6 ETREBES14 ETREBES6 ETRESES14 ETRESES6 ETREUS14 ETREUS6 RSSFE RTS16AIS RSa6=C LCRCATMX FDL-PLBOFF ETREBES NTREBES PTRNBER BPV13 BPV5 FE13 FE5 CEC13 CEC5 REC13 REC5 CNT13 CNT5 ENT13 ENT5 ETES13 ETES5 ETBES13 ETBES5 ETSES13 ETSES5 ETUS13 ETUS5 ETREES13 ETREES5 ETREBES13 ETREBES5 ETRESES13 ETRESES5 ETREUS13 ETREUS5 TSSFE LBFA RSa6=A REBIT FDL-PLBON ETREES NTREES DETECT BPV12 BPV4 FE12 FE4 CEC12 CEC4 REC12 REC4 CNT12 CNT4 ENT12 ENT4 ETES12 ETES4 ETBES12 ETBES4 ETSES12 ETSES4 ETUS12 ETUS4 ETREES12 ETREES4 ETREBES12 ETREBES4 ETRESES12 ETRESES4 ETREUS12 ETREUS4 ESE LFALR RSa6=8 ECE LLBON CMA ETUAS NTUAS NROUAS BPV11 BPV3 FE11 FE3 CEC11 CEC3 REC11 REC3 CNT11 CNT3 ENT11 ENT3 ETES11 ETES3 ETBES11 ETBES3 ETSES11 ETSES3 ETUS11 ETUS3 ETREES11 ETREES3 ETREBES11 ETREBES3 ETRESES11 ETRESES3 ETREUS11 ETREUS3 FAE LTSFA LTS0MFA CREBIT CRCE LLBOFF BFA ETSES NTSES NT1OUAS BPV10 BPV2 FE10 FE2 CEC10 CEC2 REC10 REC2 CNT10 CNT2 ENT10 ENT2 ETES10 ETES2 ETBES10 ETBES2 ETSES10 ETSES2 ETUS10 ETUS2 ETREES10 ETREES2 ETREBES10 ETREBES2 ETRESES10 ETRESES2 ETREUS10 ETREUS2 RAC LSFA LTS16MFA RJYA RTS16MFA FBE SSFA ETBES NTBES EROUAS BPV9 BPV1 FE9 FE1 CEC9 CEC1 REC9 REC1 CNT9 CNT1 ENT9 ENT1 ETES9 ETES1 ETBES9 ETBES1 ETSES9 ETSES1 ETUS9 ETUS1 ETREES9 ETREES1 ETREBES9 ETREBES1 ETRESES9 ETRESES1 ETREUS9 ETREUS1 FAC LFA RFA LFV NFA ETES NTES OUAS BPV8 BPV0 FE8 FE0 CEC8 CEC0 REC8 REC0 CNT8 CNT0 ENT8 ENT0 ETES8 ETES0 ETBES8 ETBES0 ETSES8 ETSES0 ETUS8 ETUS0 ETREES8 ETREES0 ETREBES8 ETREBES0 ETRESES8 ETRESES0 ETREUS8 ETREUS0 Y00 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y0A Y0B Y0C Y0D Y0E Y0F Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y1A Y1B Y1C Y1D Y1E Y1F Y20 Y21 Y22 Y23
FRM_SR0 FRM_SR1 FRM_SR2 FRM_SR3 FRM_SR4 FRM_SR5 FRM_SR6 FRM_SR7 FRM_SR8 FRM_SR9 FRM_SR10 FRM_SR11 FRM_SR12 FRM_SR13 FRM_SR14 FRM_SR15 FRM_SR16 FRM_SR17 FRM_SR18 FRM_SR19 FRM_SR20 FRM_SR21 FRM_SR22 FRM_SR23 FRM_SR24 FRM_SR25 FRM_SR26 FRM_SR27 FRM_SR28 FRM_SR29 FRM_SR30 FRM_SR31 FRM_SR32 FRM_SR33 FRM_SR34 FRM_SR35
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Register Maps (continued)
Table 182. Framer Unit Status Register Map (continued)
Framer Status Clear on Read (COR) Read (R) Write (W) COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR COR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address (hex) Framer 1--8 NTES15 NTES7 NTBES15 NTBES7 NTSES15 NTSES7 NTUS15 NTUS7 NTREES15 NTREES7 NTREBES15 NTREBES7 NTRESES15 NTRESES7 NTREUS15 NTREUS7 NFB1 [FI5E] 0 0 [Sa4-1] 0 [Sa4-17] RC1 [Sa5-1] RC9 [Sa5-17] RM3 [Sa6-1] 0 [Sa6-17] 0 [Sa7-1] 0 [Sa7-17] G3 [Sa8-1] FE [Sa8-17] NTES14 NTES6 NTBES14 NTBES6 NTSES14 NTSES6 NTUS14 NTUS6 NTREES14 NTREES6 NTREBES14 NTREBES6 NTRESES14 NTRESES6 NTREUS14 NTREUS6 FBI [FI3E] 0 0 [Sa4-3] 0 [Sa4-19] RC2 [Sa5-3] RC10 [Sa5-19] RA1 [Sa6-3] 0 [Sa6-19] 0 [Sa7-3] 0 [Sa7-19] LV [Sa8-3] SE [Sa8-19] NTES13 NTES5 NTBES13 NTBES5 NTSES13 NTSES5 NTUS13 NTUS5 NTREES13 NTREES5 NTREBES13 NTREBES5 NTRESES13 NTRESES5 NTREUS13 NTREUS5 A bit 0 R-0 [Sa4-5] R-0 [Sa4-21] RC3 [Sa5-5] RC11 [Sa5-21] RA2 [Sa6-5] 0 [Sa6-21] 0 [Sa7-5] 0 [Sa7-21] G4 [Sa8-5] LB [Sa8-21] NTES12 NTES4 NTBES12 NTBES4 NTSES12 NTSES4 NTUS12 NTUS4 NTREES12 NTREES4 NTREBES12 NTREBES4 NTRESES12 NTRESES4 NTREUS12 NTREUS4 Sa4 0 R-0 [Sa4-7] R-0 [Sa4-23] RC4 [Sa5-7] RSPB1 = 0 [Sa5-23] RS1 [Sa6-7] 0 [Sa6-23] 0 [Sa7-7] 0 [Sa7-23] U1 [Sa8-7] G1 [Sa8-23] NTES11 NTES3 NTBES11 NTBES3 NTSES11 NTSES3 NTUS11 NTUS3 NTREES11 NTREES3 NTREBES11 NTREBES3 NTRESES11 NTRESES3 NTREUS11 NTREUS3 Sa5 0 R-0 [Sa4-9] R-0 [Sa4-25] RC5 [Sa5-9] RSPB2 = 1 [Sa5-25] RS2 [Sa6-9] 0 [Sa6-25] 0 [Sa7-9] 0 [Sa7-25] U2 [Sa8-9] R [Sa8-25] NTES10 NTES2 NTBES10 NTBES2 NTSES10 NTSES2 NTUS10 NTUS2 NTREES10 NTREES2 NTREBES10 NTREBES2 NTRESES10 NTRESES2 NTREUS10 NTREUS2 Sa6 RX2 R-1 [Sa4-11] R-1 [Sa4-27] RC6 [Sa5-11] RSPB3 = 0 [Sa5-27] RS3 [Sa6-11] 0 [Sa6-27] 0 [Sa7-11] 0 [Sa7-27] G5 [Sa8-11] G2 [Sa8-27] NTES9 NTES1 NTBES9 NTBES1 NTSES9 NTSES1 NTUS9 NTUS1 NTREES9 NTREES1 NTREBES9 NTREBES1 NTRESES9 NTRESES1 NTREUS9 NTREUS1 Sa7 RX1 R-1 [Sa4-13] R-1 [Sa4-29] RC7 [Sa5-13] RM1 [Sa5-29] RS4 [Sa613] 0 [Sa6-29] 0 [Sa7-13] 0 [Sa7-29] SL [Sa8-13] Nm [Sa8-29] NTES8 NTES0 NTBES8 NTBES0 NTSES8 NTSES0 NTUS8 NTUS0 NTREES8 NTREES0 NTREBES8 NTREBES0 NTRESES8 NTRESES0 NTREUS8 NTREUS0 Sa8 RX0 R-1 [Sa4-15] R-1 [Sa4-31] RC8 [Sa5-15] RM2 [Sa5-31] RSPB4 = 1 [Sa6-15] 0 [Sa6-31] 0 [Sa7-15] 0 [Sa7-31] G6 [Sa8-15] Nl [Sa8-31] Y24 Y25 Y26 Y27 Y28 Y29 Y2A Y2B Y2C Y2D Y2E Y2F Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y3A Y3B Y3C Y3D Y3E Y3F
FRM_SR36 FRM_SR37 FRM_SR38 FRM_SR39 FRM_SR40 FRM_SR41 FRM_SR42 FRM_SR43 FRM_SR44 FRM_SR45 FRM_SR46 FRM_SR47 FRM_SR48 FRM_SR49 FRM_SR50 FRM_SR51 FRM_SR52 FRM_SR53 FRM_SR54* FRM_SR55* FRM_SR56* FRM_SR57* FRM_SR58* FRM_SR59* FRM_SR60* FRM_SR61* FRM_SR62* FRM_SR63*
* Unbracketed contents are valid for DS1 modes. Bracketed contents, [], are valid for CEPT mode.
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Register Maps (continued)
Receive Framer Signaling Registers (Read-Only)
The address of the registers is shown with the most significant digit, designated by Y, which is used to identify each framer (for framer 1--framer 8, Y = 2--9, respectively). Table 183. Receive Signaling Registers Map
Receive Signaling Clear on Read (COR) Read (R) Write (W)
5
Bit 7
Bit 61
Bit 51
Bit 42
Bit 33
Bit 23
Bit 14
Bit 0
Register Address (hex) Framer 1--8
FRM_RSR0
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P
G_0 G_1 G_2 G_3 G_4 G_5 G_6 G_7 G_8 G_9 G_10 G_11 G_12 G_13 G_14 G_15 G_16 G_17 G_18 G_19 G_20 G_21 G_22 G_23 X7 X X X X X X X
F_0 F_1 F_2 F_3 F_4 F_5 F_6 F_7 F_8 F_8 F_10 F_11 F_12 F_13 F_14 F_15 F_16 F_17 F_18 F_19 F_20 F_21 F_22 F_23 X X X X X X X X
E_0 E_1 E_2 E_3 E_4 E_5 E_6 E_7 E_8 E_8 E_10 E_11 E_12 E_13 E_14 E_15 E_16 E_17 E_18 E_19 E_20 E_21 E_22 E_23 E_24 E_25 E_26 E_27 E_28 E_29 E_30 E_31
D_0 D_1 D_2 D_3 D_4 D_5 D_6 D_7 D_8 D_8 D_10 D_11 D_12 D_13 D_14 D_15 D_16 D_17 D_18 D_19 D_20 D_21 D_22 D_23 D_24 D_25 D_26 D_27 D_28 D_29 D_30 D_31
C_0 C_1 C_2 C_3 C_4 C_5 C_6 C_7 C_8 C_8 C_10 C_11 C_12 C_13 C_14 C_15 C_16 C_17 C_18 C_19 C_20 C_21 C_22 C_23 C_24 C_25 C_26 C_27 C_28 C_29 C_30 C_31
B_0 B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_8 B_10 B_11 B_12 B_13 B_14 B_15 B_16 B_17 B_18 B_19 B_20 B_21 B_22 B_23 B_24 B_25 B_26 B_27 B_28 B_29 B_30 B_31
A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_8 A_10 A_11 A_12 A_13 A_14 A_15 A_16 A_17 A_18 A_19 A_20 A_21 A_22 A_23 A_24 A_25 A_26 A_27 A_28 A_29 A_30 A_31
Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y4A Y4B Y4C Y4D Y4E Y4F Y50 Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y5A Y5B Y5C Y5D Y5E Y5F
FRM_RSR1 FRM_RSR2 FRM_RSR3 FRM_RSR4 FRM_RSR5 FRM_RSR6 FRM_RSR7 FRM_RSR8 FRM_RSR9 FRM_RSR10 FRM_RSR11 FRM_RSR12 FRM_RSR13 FRM_RSR14 FRM_RSR15 FRM_RSR165 FRM_RSR17 FRM_RSR18 FRM_RSR19 FRM_RSR20 FRM_RSR21 FRM_RSR22 FRM_RSR23 FRM_RSR242 FRM_RSR25
2
FRM_RSR262 FRM_RSR272 FRM_RSR282 FRM_RSR292 FRM_RSR302 FRM_RSR31
2
1. In the DS1 robbed-bit signaling modes, these bits are copied from the corresponding transmit signaling registers. In the CEPT signaling mo des, these bits are in the 0-state and should be ignored. 2. In the DS1 signaling modes, these registers contain unknown data. 3. In DS1 4-state and 2-state signaling, these bits contain unknown data. 4. In DS1 2-state signaling, these bits contain unknown data. 5. In the CEPT signaling modes, the A-, B-, C-, D-, and P-bit information of these registers contains unknown data. 6. Signifies unknown data.
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Preliminary Data Sheet October 2000
Register Maps (continued)
Framer Unit Parameter Register Map
The address of the registers is shown with the most significant digit, designated by Y, which is used to identify each framer (for framer 1--framer 8, Y = 2--9, respectively). Table 184. Framer Unit Parameter Register Map
Framer Control Clear on Read (COR) Read (R) Write (W)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Address (hex) Framer 1--8
FRM_PR0 FRM_PR1 FRM_PR2 FRM_PR3 FRM_PR4 FRM_PR5 FRM_PR6 FRM_PR7 FRM_PR8 FRM_PR9 FRM_PR10
SLCIE (0) SR1B7IE (0) SR2B7IE (0) SR3B7IE (0) SR4B7IE (0) SR5B7IE (0) SR6B7IE (0) SR7B7IE (0) LC2 (1) CRCO7 (0) ESM1 (0) EST7 (0) SEST15 (0) SEST7 (0) 0 ETRESa6-F (0) NTSa6-C (0) 0 0 AFDPLBE (0) TICRC (0)
Reserved (0) SR1B6IE (0) SR2B6IE (0) SR3B6IE (0) SR4B6IE (0) SR5B6IE (0) SR6B6IE (0) SR7B6IE (0) LC1 (1) CRCO6 (0) ESM0 (0) EST6 (0) SEST14 (0) SEST6 (0) 0 ETRESa6-E (0) 0 0 0 AFDLLBE (0) TLIC (0)
RSRIE (0) SR1B5IE (0) SR2B5IE (0) SR3B5IE (0) SR4B5IE (0) SR5B5IE (0) SR6B5IE (0) SR7B5IE (0) LC0 (0) CRCO5 (0) RABF (0) EST5 (0) SEST13 (0) SEST5 (0) 0 ETRESa6-8 (0) NTSa6-8 (0) 0 0 Reserved (0) TLLBOFF (0)
TSRIE (0) SR1B4IE (0) SR2B4IE (0) SR3B4IE (0) SR4B4IE (0) SR5B4IE (0) SR6B4IE (0) SR7B4IE (0) FMODE4 (0) CRCO4 (0) Reserved (0) EST4 (0) SEST12 (0) SEST4 (0) 0 ETRERFA (0) 0 NTRERFA (0) 0 ALLBE (0) TLLBON (0)
SR567IE (0) SR1B3IE (0) SR2B3IE (0) SR3B3IE (0) SR4B3IE (0) SR5B3IE (0) SR6B3IE (0) SR7B3IE (0) FMODE3 (0) CRCO3 (0) CNUCLBEN (0) EST3 (0) SEST11 (0) SEST3 (0) ETSLIP (0) ETRESLIP (0) NTSLIP (0) NTRESLIP (0) NTRESa6-C (0) TSAIS (0) TQRS (0)
SR34IE (0) SR1B2IE (0) SR2B2IE (0) SR3B2IE (0) SR4B2IE (0) SR5B2IE (0) SR6B2IE (0) SR7B2IE (0) FMODE2 (0) CRCO2 (0) FEREN [NFFE] * (0) EST2 (0) SEST10 (0) SEST2 (0) ETAIS (0) ETREAIS (0) NTAIS (0) NTREAIS (0) NTRESa6-F (0) Reserved (0) TPRS (0)
SR2IE (0) SR1B1IE (0) SR2B1IE (0) SR3B1IE (0) SR4B1IE (0) SR5B1IE (0) SR6B1IE (0) SR7B1IE (0) FMODE1 (0) CRCO1 (0) AISM (0) EST1 (0) SEST9 (0) SEST1 (0) ETLMFA (0) ETRELMFA (0) NTLMFA (0) NTRELMFA (0) NTRESa6-E (0) ASAISTMX (0) TUFAUXP (0)
SR1IE (0) SR1B0IE (0) SR2B0IE (0) SR3B0IE (0) SR4B0IE (0) SR5B0IE (0) SR6B0IE (0) SR7B0IE (0) FMODE0 (0) CRCO0 (0) SSa6M (0) EST0 (0) SEST8 (0) SEST0 (0) ETLFA (0) ETRELFA (0) NTLFA (0) NTRELFA (0) NTRESa6-8 (0) ASAIS (0) TUFAIS (0)
Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y6A
FRM_PR11 FRM_PR12 FRM_PR13 FRM_PR14 FRM_PR15 FRM_PR16 FRM_PR17 FRM_PR18 FRM_PR19 FRM_PR20
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Y6B Y6C Y6D Y6E Y6F Y70 Y71 Y72 Y73 Y74
* Definition in CEPT mode.
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Register Maps (continued)
Table 184. Framer Unit Parameter Register Map (continued)
Framer Control Clear on Read (COR) Read (R) Write (W)
R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Address (hex) Framer 1--8
FRM_PR21 FRM_PR22 FRM_PR23 FRM_PR24 FRM_PR25 FRM_PR26 FRM_PR27 FRM_PR28
TC/R=1 (0) TLIC7 (0) SSTSC7 (0) LBC2 (0) Reserved (0) Reserved (0) TRFA (0) 0
TFDLC (0) TLIC6 (1) SSTSC6 (1) LBC1 (0) SLBC1 (0) Reserved (0) TJRFA (0) 0
TFDLSAIS (0) TLIC5 (1) SSTSC5 (1) LBC0 (0) SLBC0 (0) SYSFSM (0) AARSa6_C (0) ATERTX (0) SaS5 (0) Reserved (0) X-0 Sa4-5 X-0 Sa4-21 XC3 Sa5-5 XC11 Sa5-21 XA2 Sa6-5 Sa6-21 Sa7-5 Sa7-21 Sa8-5 Sa8-21 TLTS16RMFA (0)
TFDLLAIS (0) TLIC4 (1) SSTSC4 (1) TSLBA4 (0) STSLBA4 (0) TFM2 (0) AARSa6_8 (0) ATELTS0MFA (0) TSa8 (0) TESa8 (0) X-0 Sa4-7 X-0 Sa4-23 XC4 Sa5-7 XSPB1 = 0 Sa5-23 XS1 Sa6-7 Sa6-23 Sa7-7 Sa7-23 Sa8-7 Sa8-23
ALTTS16RMFA (0)
Reserved (0) TLIC3 (1) SSTSC3 (1) TSLBA3 (0) STSLBA3 (0) TFM1 (0) ATMX (0) ATECRCE (0) TSa7 (0) TESa7 (0) X-0 Sa4-9 X-0 Sa4-25 XC5 Sa5-9 XSPB2 = 1 Sa5-25 XS2 Sa6-9 Sa6-25 Sa7-9 Sa7-25 Sa8-9 Sa8-25 XS (0)
Reserved (0) TLIC2 (1) SSTSC2 (1) TSLBA2 (0) STSLBA2 (0) FRFRM (0) AAB0LMFA (0) TSiNF (0) TSa6 (0) TESa6 (0) X-1 Sa4-11 X-1 Sa4-27 XC6 Sa5-11 XSPB3 = 0 Sa5-27 XS3 Sa6-11 Sa6-27 Sa7-11 Sa7-27 Sa8-11 Sa8-27 TTS16X2 (0)
Reserved (0) TLIC1 (1) SSTSC1 (1) TSLBA1 (0) STSLBA1 (0) SWRESTART (0) AAB16LMFA (0) TSiF (0) TSa5 (0) TESa5 (0) X-1 Sa4-13 X-1 Sa4-29 XC7 Sa5-13 XM1 Sa5-29 XS4 Sa613 Sa6-29 Sa7-13 Sa7-29 Sa8-13 Sa8-29 TTS16X1 (0)
Reserved (0) TLIC0 (1) SSTSC0 (1) TSLBA0 (0) STSLBA0 (0) SWRESET (0) ARLFA (0) SIS, T1E (0) TSa4 (0) TESa4 (0) X-1 Sa4-15 X-1 Sa4-31 XC8 Sa5-15 XM2 Sa5-31 XSPB4 = 1 Sa6-15 Sa6-31 Sa7-15 Sa7-31 Sa8-15 Sa8-31 TTS16X0 (0)
Y75 Y76 Y77 Y78 Y79 Y7A Y7B Y7C
FRM_PR29 FRM_PR30 FRM_PR31 FRM_PR32 FRM_PR33 FRM_PR34 FRM_PR35 FRM_PR36 FRM_PR37 FRM_PR38 FRM_PR39 FRM_PR40 FRM_PR41
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
SaS7 (0) TDNF (0) 0 Sa4-1 0 Sa4-17 XC1 Sa5-1 XC9 Sa5-17 XM3 Sa6-1 Sa6-17 Sa7-1 Sa7-17 Sa8-1 Sa8-17 Reserved (0)
SaS6 (0) Reserved (0) 0 Sa4-3 0 Sa4-19 XC2 Sa5-3 XC10 Sa5-19 XA1 Sa6-3 Sa6-19 Sa7-3 Sa7-19 Sa8-3 Sa8-19 TLTS16AIS (0)
Y7D Y7E Y7F Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89
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Preliminary Data Sheet October 2000
Register Maps (continued)
Table 184. Framer Unit Parameter Register Map (continued)
Framer Control Clear on Read (COR) Read (R) Write (W)
R/W R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Address (hex) Framer 1--8
FRM_PR42 FRM_PR43
FEX7 (0) Reserved (0) TCSS (0) HWYEN (0) RFE (0) Reserved (0) Reserved (0) TTSE31 (0) TTSE23 (0) TTSE15 (0) TTSE7 (0) RTSE31 (0) RTSE23 (0) RTSE15 (0) RTSE7 (0) THS31 (0) THS23 (0) THS15 (0) THS7 (0) RHS31 (0) RHS23 (0) RHS15 (0) RHS7 (0) Reserved (0) Reserved (0) Reserved Reserved GPTRN3 (0) DPTRN3 (0)
FEX6 (0) Reserved (0) ASTSAIS (0) Reserved (0) ROFF2 (0) TCE (0) RCE (0) TTSE30 (0) TTSE22 (0) TTSE14 (0) TTSE6 (0) RTSE30 (0) RTSE22 (0) RTSE14 (0) RTSE6 (0) THS30 (0) THS22 (0) THS14 (0) THS6 (0) RHS30 (0) RHS22 (0) RHS14 (0) RHS6 (0) Reserved (0) Reserved (0) Reserved Reserved GPTRN2 (0) DPTRN2 (0)
FEX5 (0) Reserved (0) TSR-ASM (0) Reserved (0) ROFF1 (0) TBYOFF5 (0) RBYOFF5 (0) TTSE29 (0) TTSE21 (0) TTSE13 (0) TTSE5 (0) RTSE29 (0) RTSE21 (0) RTSE13 (0) RTSE5 (0) THS29 (0) THS21 (0) THS13 (0) THS5 (0) RHS29 (0) RHS21 (0) RHS13 (0) RHS5 (0) Reserved (0) Reserved (0) Reserved Reserved GPTRN1 (0) DPTRN1 (0)
FEX4 (0) Reserved (0) MOS (0) CHIMM (0) ROFF0 (0) TBYOFF4 (0) RBYOFF4 (0) TTSE28 (0) TTSE20 (0) TTSE12 (0) TTSE4 (0) RTSE28 (0) RTSE20 (0) RTSE12 (0) RTSE4 (0) THS28 (0) THS20 (0) THS12 (0) THS4 (0) RHS28 (0) RHS20 (0) RHS12 (0) RHS4 (0) Reserved (0) Reserved (0) Reserved Reserved GPTRN0 (0) DPTRN0 (0)
FEX3 (0) SSC (0) RSI (0) CDRS1 (0) TFE (0) TBYOFF3 (0) RBYOFF3 (0) TTSE27 (0) TTSE19 (0) TTSE11 (0) TTSE3 (0) RTSE27 (0) RTSE19 (0) RTSE11 (0) RTSE3 (0) THS27 (0) THS19 (0) THS11 (0) THS3 (0) RHS27 (0) RHS19 (0) RHS11 (0) RHS3 (0) Reserved (0) Reserved (0) Reserved Reserved GFRMSEL (0) DUFTP (0)
FEX2 (0) STS2 [SaFDL2] (0) ASM (0) CDRS0 (0) TOFF2 (0) TBYOFF2 (0) RBYOFF2 (0) TTSE26 (0) TTSE18 (0) TTSE10 (0) TTSE2 (0) RTSE26 (0) RTSE18 (0) RTSE10 (0) RTSE2 (0) THS26 (0) THS18 (0) THS10 (0) THS2 (0) RHS26 (0) RHS18 (0) RHS10 (0) RHS2 (0) Reserved (0) Reserved (0) Reserved Reserved GBLKSEL (0) DBLKSEL (0)
FEX1 (0) STS1 [SaFDL1] (0) STOMP (0) CMS (0) TOFF1 (0) TBYOFF1 (0) RBYOFF1 (0) TTSE25 (0) TTSE17 (0) TTSE9 (0) TTSE1 (0) RTSE25 (0) RTSE17 (0) RTSE9 (0) RTSE1 (0) THS25 (0) THS17 (0) THS9 (0) THS1 (0) RHS25 (0) RHS17 (0) RHS9 (0) RHS1 (0) TCHIDTS (0) RCHIDTS (0) Reserved Reserved TPEI (0) reserved (0)
FEX0 (0) STS0 [SaFDL0] (1) TSIG (0) HFLF (0) TOFF0 (0) TBYOFF0 (0) RBYOFF0 (0) TTSE24 (0) TTSE16 (0) TTSE8 (0) TTSE0 (0) RTSE24 (0) RTSE16 (0) RTSE8 (0) RTSE0 (0) THS24 (0) THS16 (0) THS8 (0) THS0 (0) RHS24 (0) RHS16 (0) RHS8 (0) RHS0 (0) TBYOFF6 (0) RBYOFF6 (0) Reserved Reserved ITD (0) IRD (0)
Y8A Y8B
FRM_PR44 FRM_PR45 FRM_PR46 FRM_PR47 FRM_PR48 FRM_PR49 FRM_PR50 FRM_PR51 FRM_PR52 FRM_PR53 FRM_PR54 FRM_PR55 FRM_PR56 FRM_PR57 FRM_PR58 FRM_PR59 FRM_PR60 FRM_PR61 FRM_PR62 FRM_PR63 FRM_PR64 FRM_PR65 FRM_PR66 FRM_PR67 FRM_PR68 FRM_PR69 FRM_PR70
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- -- R/W R/W
Y8C Y8D Y8E Y8F Y90 Y91 Y92 Y93 Y94 Y95 Y96 Y97 Y98 Y99 Y9A Y9B Y9C Y9D Y9E Y9F YA0 YA1 YA2 YA3 YA4 YA5 YA6
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Preliminary Data Sheet October 2000
TFRA08C13 OCTAL T1/E1 Framer
Register Maps (continued)
Transmit Signaling Registers (Read/Write)
The address of the registers is shown with the most significant digit, designated by Y, which is used to identify each framer (for framer 1--framer 8, Y = 2--9, respectively). Table 185. Transmit Signaling Registers Map
Transmit Signaling Clear on Read (COR) Read (R) Write (W) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 Bit 61 Bit 51 Bit 42 Bit 33 Bit 23 Bit 14 Bit 0 Register Address (hex) Framer 1--8 P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P G_0 G_1 G_2 G_3 G_4 G_5 G_6 G_7 G_8 G_9 G_10 G_11 G_12 G_13 G_14 G_15 G_16 G_17 G_18 G_19 G_20 G_21 G_22 G_23 X7 X X X X X X X F_0 F_1 F_2 F_3 F_4 F_5 F_6 F_7 F_8 F_8 F_10 F_11 F_12 F_13 F_14 F_15 F_16 F_17 F_18 F_19 F_20 F_21 F_22 F_23 X X X X X X X X -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D_0 D_1 D_2 D_3 D_4 D_5 D_6 D_7 D_8 D_8 D_10 D_11 D_12 D_13 D_14 D_15 D_16 D_17 D_18 D_19 D_20 D_21 D_22 D_23 D_24 D_25 D_26 D_27 D_28 D_29 D_30 D_31 C_0 C_1 C_2 C_3 C_4 C_5 C_6 C_7 C_8 C_8 C_10 C_11 C_12 C_13 C_14 C_15 C_16 C_17 C_18 C_19 C_20 C_21 C_22 C_23 C_24 C_25 C_26 C_27 C_28 C_29 C_30 C_31 B_0 B_1 B_2 B_3 B_4 B_5 B_6 B_7 B_8 B_8 B_10 B_11 B_12 B_13 B_14 B_15 B_16 B_17 B_18 B_19 B_20 B_21 B_22 B_23 B_24 B_25 B_26 B_27 B_28 B_29 B_30 B_31 A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_8 A_10 A_11 A_12 A_13 A_14 A_15 A_16 A_17 A_18 A_19 A_20 A_21 A_22 A_23 A_24 A_25 A_26 A_27 A_28 A_29 A_30 A_31 YE0 YE1 YE2 YE3 YE4 YE5 YE6 YE7 YE8 YE9 YEA YEB YEC YED YEE YEF YF0 YF1 YF2 YF3 YF4 YF5 YF6 YF7 YF8 YF9 YFA YFB YFC YFD YFE YFF
FRM_TSR05 FRM_TSR1 FRM_TSR2 FRM_TSR3 FRM_TSR4 FRM_TSR5 FRM_TSR6 FRM_TSR7 FRM_TSR8 FRM_TSR9 FRM_TSR10 FRM_TSR11 FRM_TSR12 FRM_TSR13 FRM_TSR14 FRM_TSR15 FRM_TSR165 FRM_TSR17 FRM_TSR18 FRM_TSR19 FRM_TSR20 FRM_TSR21 FRM_TSR22 FRM_TSR23 FRM_TSR246 FRM_TSR25 FRM_TSR27
6
FRM_TSR266
6
FRM_TSR286 FRM_TSR296 FRM_TSR306 FRM_TSR316
1. In the normal DS1 robbed-bit signaling modes, these bits define the corresponding receive channel signaling mode and are copied into the received signaling registers. In the CEPT signaling modes, these bits are ignored. 2. These bits contain unknown data. 3. In DS1 4-state and 2-state signaling modes, these bits contain unknown data. 4. In DS1 2-state signaling mode, these bits contain unknown data. 5. In the CEPT signaling modes, the A-, B-, C-, D-, and P-bit information of these registers contains unknown data. 6. In the DS1 signaling modes, these registers contain unknown data. 7. Signifies known data.
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Register Maps (continued)
Facility Data Link Parameter/Control and Status Registers (Read-Write)
Table 186. Facility Data Link Register Map
Transmit Signaling Clear on Read (COR) Read (R) Write (W) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Address* (hex) FDL 1 FDL 3 FDL 5 FDL 7 FRANSIT3 (1) FTPRM (0) FTBCRC (0) FTFC (0) FTD7 (0) FTIC7 (0) FRANSIE (0) Reserved FRMC7 (0) Reserved (0) FTANSI (0) FRANSI FTED FREOF 0 FRD7 (0) FRANSIT2 (0) FRPF (0) FRIIE (0) FTABT (0) FTD6 (0) FTIC6 (0) Reserved (0) Reserved FRMC6 (0) FTM (0) Reserved (0) FRIDL FTQS6 FRQS6 0 FRD6 (0) FRANSIT1 (1) FTR (0) FROVIE (0) FTIL5 (0) FTD5 (0) FTIC5 (0) FRIL5 (0) Reserved FRMC5 (0) FMATCH (0) FTANSI5 (0) FROVERUN FTQS5 FRQS5 X5 FRD5 (0) FRANSIT0 (0) FRR (0) FREOFIE (0) FTIL4 (0) FTD4 (0) FTIC4 (0) FRIL4 (0) Reserved FRMC4 (0) FALOCT (0) FTANSI4 (0) FREOF FTQS4 FRQS4 X4 FRD4 (0) Reserved (0) FTE (0) FRFIE (0) FTIL3 (0) FTD3 (0) FTIC3 (0) FRIL3 (0) Reserved FRMC3 (0) FMSTAT (0) FTANSI3 (0) FRF FTQS3 FRQS3 X3 FRD3 (0) Reserved (0) FRE (0) FTUNDIE (0) FTIL2 (0) FTD2 (0) FTIC2 (0) FRIL2 (0) Reserved FRMC2 (0) FOCTOF2 (0) FTANSI2 (0) FTUNDAB T FTQS2 FRQS2 X2 FRD2 (0) FLAGS (0) FLLB (0) FTEIE (0) FTIL1 (0) FTD1 (0) FTIC1 (0) FRIL1 (0) Reserved FRMC1 (0) FOCTOF1 (0) FTANSI1 (0) FTEM FTQS1 FRQS1 X1 FRD1 (0) FDINT (0) FRLB (0) FTDIE (0) FTIL0 (0) FTD0 (0) FTIC0 (0) FRIL0 (0) Reserved FRMC0 (0) FOCTOF 0 (0) FTANSI0 (0) FTDONE FTQS0 FRQS0 X0 FRD0 (0) Y00 Y01 Y02 Y03 Y04 Y05 Y06 -- Y08 Y09 FDL 2 FDL 4 FDL 6 FDL 8 Y20 Y21 Y22 Y23 Y24 Y25 Y26 -- Y28 Y29
FDL_PR0 FDL_PR1 FDL_PR2 FDL_PR3 FDL_PR4 FDL_PR5 FDL_PR6 FDL_PR7 FDL_PR8 FDL_PR9
R/W R/W R/W R/W R/W R/W R/W Reserved R/W R/W
FDL_PR1 0 FDL_SR0 FDL_SR1 FDL_SR2 FDL_SR3 FDL_SR4
R/W COR R R R R
Y0A Y0B Y0C Y0D Y0E Y07
Y2A Y2B Y2C Y2D Y2E Y27
* For FDL 1 and FDL 2, Y = A; for FDL 3 and FDL 4, Y = B; for FDL 5 and FDL 6, Y = C; for FDL 7 and FDL 8, Y = D.
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Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter VDD Supply Voltage Range Power Dissipation (Total) Maximum Voltage (Digital Pins) Minimum Voltage (Digital Pins) with Respect to GRND Storage Temperature Range Ambient Operating Temperature Range Symbol VDD PD -- -- Tstg TA Min -0.5 0.65 -- -0.5 -65 -40 Max 3.6 1.0 5.5* -- 125 85 Unit V W V V C C
* This maximum rating only applies when the device is powered up with VDD.
Operating Conditions
Parameter Power Supply High-Level Input Voltage Low-Level Input Voltage Ambient Temperature Symbol VDD VIH VIL TA Min 3.14 VDD - 1.0 0 -40 Typ 3.3 -- -- -- Max 3.47 5.25 1.0 85 Unit V V V C
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM) and charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in the defined model. No industry-wide standard has been adopted for the CDM. However, a standard HBM (resistance = 1500 W, capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using these circuit parameters. Table 187. ESD Threshold Voltage Device TFRA08C13 Voltage >1000 V
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Electrical Characteristics
Logic Interface Characteristics
Table 188. Logic Interface Characteristics (TA = -40 C to +85 C, VDD = 3.3 V 5%, VSS = 0) Parameter Input Leakage Current All Inputs Except PulledUp and Pulled-Down Pins Pulled-Up Pins Pulled-Down Pins Output Voltage: Low High Input Capacitance Load Capacitance: All Outputs Except D[7:0] D[7:0]
* Sinking. Sourcing. Notes: All buffers use CMOS levels. All inputs are driven between 2.4 V and 0.4 V. An internal pull-up is provided on the 3-STATE, RESET, DS1/CEPT, MPMODE, CS, MPCK, TDI, TCK, and TMS pins. An internal pull-down is provided on the TRST pin.
Symbol IL ILPU ILPD VOL VOH CI CL CL
Test Conditions -- -- -- IOL = - 5.0 mA* IOH = 5.0 mA -- -- --
Min -- -- -- 0 VDD - 1.0 -- -- --
Max 10 80 185 0.5 VDD 3.0 50 100
Unit A A A V V pF pF pF
Power Supply Bypassing
External bypassing is required for each power supply pin. A 0.1 F capacitor must be connected between each VDD and VSS, between VDDD and VSSD, and between VDDA and VSSA. The VSS, VSSD, and VSSA planes should be separated, joining at a single point near the external ground connection. The need to reduce high-frequency coupling into the analog supply (VDDA) and quiet digital supply (VDDD) may require inductive beads to be inserted between these lines and the 3.3 V power plane. Capacitors used for power supply bypassing should be placed as close as possible to the device pins.
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Outline Diagram
352-Pin PBGA
Dimensions are in millimeters.
35.00 0.20 A1 BALL IDENTIFIER ZONE +0.70 30.00 -0.00
30.00 +0.70 -0.00 35.00 0.20
MOLD COMPOUND PWB 0.56 0.06 1.17 0.05 2.33 0.21 SEATING PLANE 0.20 0.60 0.10 SOLDER BALL 25 SPACES @ 1.27 = 31.75
AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
0.75 0.15
25 SPACES @ 1.27 = 31.75
A1 BALL CORNER
1 2 3 4 5 6 7 8 9 10
12 14 16 18 20 22 24 26 11 13 15 17 19 21 23 25
5-4407(F).ar.4
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Ordering Information
Device Code TFRA08C13 - DB Package 352-Pin PBGA Temperature -40 C to +85 C Comcode (Ordering Number) 108269754
http://www.lucent.com/micro, or for FPGA information, http://www.lucent.com/orca INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P. R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc.
October 2000 DS00-190PDH (Replaces DS99-039T1E1)

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